Program Manual for Hitachi Analogue Computer — Automatic Programming (Technical Information Series No. 5)
HITACHI Analog-Hybrid Computer
Technical Information Series No.5
PROGRAM MANUAL FOR HITACHI ANALOGUE COMPUTER
— AUTOMATIC PROGRAMING—
1968
_ Hitachi, Ltd.
printed in Japan
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CONTENTS
CONIA
Page
sceeriphon veveasssenesennsasnnnnssssssssss 55 1
Logic Operation Circuit eerrerrrtt eee eee eee eee eee ee TS . 5
2.1. Memory element «errr errr 5
2.2. Logic circuit for mode controls serrrrre Deen ew eeerenete een 7
2.3. Other logic circuits for mode control «+++: eee eeeeeeee tee eeee 12
2.4, Logic circuit for analysis of poundary value problem «errr t* oe 13
2.5, Logic circuit for analysis of extreme value problem .+rerttt'* eee 15
2,6, Time sharing computation -«+++*'* cee e eee eeennet teeeereee wenee 24
Exercises for Automatic Programing -errrrrr ewe ee eettt weeee 26
3.1, Boundary value problem serrrrtt tt" ee . 26
3.2, Extreme value problem , eee eee eenrnn? eee ee eeneee . seeeeee 31
3,3, Time sharing computation .-rrerrrett veces ve eeees . 35
1. Description
An automatic system is defined as a system which automatically analyzes problems
pertaining to so-called parameter optimization such as problems of boundary value,
extreme value, etc. which in the past usually had to be solved by a trial method when
using conventional analogue computers. In this system, a digital logic element is added to
the analogue computer, With this arrangement, it is possible to analyze those complicated
problems, and the various settings and controls which have been conventionally performed
under manual operations can now be performed automatically, thereby increasing the func-
tional capability of computation, The method of programing to which this system is
applied is called Automatic Programing. It has been said that obtaining an initial value or
unknown coefficient to have a given equation satisfy the rated boundary conditions is some-
how troublesome and even time waisting. Under an automatic system, however, the
entirely mechanical operation (called Trial Method) which was conventionally performed by
human beings is now entirely performable by an automatic system, For example, when
deciding a unknown parameter included in an equation by boundary conditions, the parameter
is properly and temporarily decided, computation is performed based on the temporary
parameter, the difference between the results of the computation and the boundary value is
detected, the parameter is automatically corrected by the computer itself with a proper
evaluating function, and the computation is reperformed, The value of the parameter is
gradually converged to the true value by repeating such operations as described above.
However, when performing programing to which this automatic system is applied, some
basic knowledge pertaining to the logic operation circuit on an analogue computer is re-
quired. At the same time, it must be so remembered that a considerably high programing
technique is required when numbers of unknown parameters are involved, The following
are analysis examples achieved by various solution method. In the following examples, an
equation of a boundary value having only one variation is used.
(Example)
y''+ ay! + 4y = 0
Wott
Obtaining value of ''a'' with which the following conditions are satisfied:
y = 0.5, y'=0 when t=0
y = 0.1, y'=Q when t=ti
(Solution)
(1) Manually correcting operation
(Trial method)
In Fig. 1.1, block diagram, the value of 'a'' is sought by a trial and error method
through computations one by one.
Fig. 1.1 Block Diagram by Trial Method
When an analogue computer which has high speed repetitive operation capability is
used, solving a problem is possible even for 2 to 3 parameters. However, when
employing a low-speed type analogue computer, solution of multiple variations is
practically impossible.
Method in which an automatic system is used.
In this method, a computing group to correct parameter is required in addition to
the main computing group.
TT 7
| i]
|
| 0.2
10
I Is,
| Yo |
| | p---— === === === -- p=
{
| 1 |
l iF
a 7 l
] : 4) A oa}
tA group Absol cal ot .
Loo solute value circuit |
0.2
Boundary
value
+1
B group
Fig. 1.2 Block Diagram in which Automatic System is Applied
In Fig. 1.2 above, the computing modules which belong to the A group compose the
main computing circuit which resolves the given equation, and the B group is an
auxiliary computing circuit which performs correcting of parameter "a".
Mode controls of the A and B groups can be made independently, and mode controls
of the these two groups pertaining to this equation are decided as shown in the table
in Fig. 1.2. More specifically, when starting computation, the value of the para-
meter "'a'' is held to any desired value (zero-volt in this case), and the A group is
computed. Next, the A group is temperarily held, the difference between the value
of the held "-2y" and '+0,2 (+20V) -- the boundary value -- is detected by summer
''AQ3", and this value is corrected and integrated by the integrator unit ''A04",
After integrating for a certain time, "'a'' is held again, and the A group performs
computation for a ''t.:'' second again based on the newly corrected value of "al. As
described above, low-speed computations are repeated, and the final value of ''a”
will be obtained.
R: Reset
C: Compute
H: Hold
Now, referring to the terminations on the patch board, how to prepare a logic con-
trol mode is explained below.
For A group integrator For B. group integrator
unit control unit control
*O R R R R "O
M
M RY Me MM RY MC
Cc C Cc H C Cc t Cc H
When Mode Control (MC) is controlled by timer TM-251:
(3) Sample hold system
Sample Hold Device (it is possible to assemble this device on a patch board by using
general purpose amplifiers) is employed in this system, combined with a repetitive
operation for having a correcting operation.
The flow chart is a shown below.
High-speed repetitive
operation group Changing parameter Low-speed operation group
; —_——_o
(Multiplier output) (for changing parameter)
y+ ay+ 4y=0
oe ee eee ee eee 4
t
: Comparat Gate
parato circuit
y(t) yt=ty
Sampling Hold
circuit circuit
Loupe-—------—
Fig. 1.4 Automatic Operation by Sample Hold:System
-3-
err ——“(—isi—ss—s—C
The features of this system are that speed available to approach an unknown para-~
meter is extremely high (since the main operational group is operated under high
speed), and that a logic circuit can be established comparatively rather simply by
using a special unit in the portion encircled by a dotted line. It may be slightly
complicated; however, a circuit diagram when a sampling hold unit is assembled
on a patch board is shown in Fig. 1.5. ,
v
A: High-speed repeti-
tive operation
B.C : Compute
0.8 = os
Comparator
Fig. 1.5 Program Utilizing Sample Hold Circuit
2. Logic Operation Circuit
Both description and types of basic logic circuits used in automatic programing are
limited in some ranges, and they consist of several kinds of memory elements (mainly inte-
grators), a operation control circuit, a relay circuit, and so on,
2.1 Memory element
(1) Trank hold
In this hold system, the IC input terminal of the integrator is utilized as a primary
delay circuit, and this system has the functions shown in the following diagram,
X
i ' i
' ;
' ! nput
oO ! t T Ic
! 1 Input waveform
' | Output
1 f
|
' i} 7
‘ '
oO \ i T
} t
RESET! HOLD ! RESET} poe waveform
| Track | | Track, |
(2) Sample hold
In this system, there are two different ways to compose the circuit. One is exactly
the same as the track hold as far as the circuit is concerned. However, setting can
be made freely by combining an integrator and operational impedance. Moreover, a
similar circuit can be composed by combining an inverter with a relay. The rela-
tions between operation mode and the sample/hold are shown below.
, C
Follw-up Memorize
R;
oe Integrator COMPUTE HOLD
Input Output
Re Inveter Relay ON Relay OFF
Fig. 2,2 Sample Hold Circuit
The other sample hold circuit is shown in Fig. 2.3, in which one integrator unit and
two summers are used. However, operations (COMP - FOLLOW-UP and HOLD-~
MEMORY) are the same.
Input
Fig. 2.3 Sample Hold Circuit
In this diagram, the follow-up time constant is 0.0015; thus, it should be noted that
the hold characteristics become unsatisfactory when this time constant is excessively
reduced. In addition to the above, a sample hold can be performed simply by using
an electronic switch, Type CP-153, High-Speed Comparator.
(3) Maximum value holder
In this circuit, maximum value of the input signal can always be obtained on the output
by applying a signal to the input. For example, when a signal as shown in Fig. 2. 4(a)
is applied to the input, the output waveform appears as shown in (b). Also, there
are three different ways in which the method can compose this circuit, as illustrated
in Fig. 2.5(a), (b), and (c).
x
(a)
|
|
I
| |
I |
ot T
Xmax\| Input waveform
I
(b)
I
0 Output waveform Ai
1
Fig. 2.4 Input and Output of NX
Maximum Value Holder
fo)
Xmax
Fig. 2.5(a) Maximum Value
Holder Circuit
1 .
+x c
1
: 1 >. al SJ Xmax
X max
Fig. 2.5(b) Maximum Value Fig. 2.5(c) Maximum Value.
Holder Circuit 2 Holder Circuit
2.2 Logic circuit for operation control
The methods of controlling repetitive operation can be classified into the following
three types: ;
Method using a timer
Method using a digital logic panel
Method combining a DC amplifier and a comparator
The method in which a timer is used is extremely simple; consequently, in this manual,
only the remaining two methods will be explained.
(1) Reset-ti-second and Comp-tz-second Repetitive Operation
Reset time cannot be freely set on TM-253 timer. However, it is possible when a
TM-251 timer is used. When no TM-251 is available, both Reset and Comp times can
be made into a freely independent variable by using a potentiometer and employing the
circuit illustrated in Fig. 2.7. Repeating calculations are started as soon as the
function switch is set from RESET to START.
COMPUTE
RESET
(a)
Function switch +1
i eo
y
+1} —-~——---~--,---~---—~—~— ~~~
i
5 ; |
! I
' 1
t |
0 ' Y * + t
|
R a |
elay operation Ld Sccondele_K ele Second \ (b)
K | Secondl K \ 1 |
RESET COMPUTE, = RESET COMPUTE! RESET |
H 1
I '
OFF oN (OFF on OFF
" Fig. 2.7 Reset Comp Repetitive Operation Control
-7-
(2) Reset-t:, Comp-t., Hold-t; Secon Repetive Operation
With this logic circuit, it is possible to perform repetitive operations of Reset-Comp-
Hold; also it is feasible to freely set the individual control mode times.
* Wiring of 1 (Refer to Fig. 2.7 and Fig. 2. 8)
&
10 10 1
5B He
RO 1
‘Gxte6) O
ere
1 100
fF
R
@=x§)
n
oe
<
—
—
=)
S
Ss
ZO10°
“O20 10
ole ¢
L °F
RR Output
“19
03
HOLD
COMPUTE
cP RESET
—~1 | >| #o1ipe-e-scenecnce
K2
|
| ea
I
CP
___
|
“ |
K3 ! 1
| | &
j
|
Kop 4 ---41--| 4-4
RESET TIME _ t; = K,/K, See. |
COMPUTE TIME t, = K;—K2/K, Sec. Lt
HOLD TIME t; = 1—K,/K, See. | fod roy
' 1; ! 1 |
H i}
RESET Sig. t
I
COMPUTE Sig. ee ee
' !
HOLD Sig. Lu! C1! oo
R Cc HR c HR
Fig. 2.8 Reset-COMP-Hold Repetitive Operation Logic
Circuit and Operating Principle Diagram
The control is started as soon as the function switch is set to START in this theoretical
circuit, in a manner identical to (1) above.
The individual mode times are shown above.
f (3)
Logic Circuit for Repetitive Operation
Using time is decided through a combination of counter, logic gate and flip-flop; and by
operating the ring counter, different controls having any desired time width within ten
types can be produced. Deciding the individual control times:
Time
Setting Time Total Time Necessary Operation
Product
0 0.16 Second 0.16 Second MAIN RESET
1 0.28 Second 0. 44 Second MAIN COMPUTER
2 0.05 Second 0.49 Second MAIN HOLD
3 0.21 Second 0.70 Second B GROUP COMPUTE
4 0.33 Second 1.03 Second B GROUP HOLD
5 0.10 Second 1,13 Second MAIN RESET
6 0.26 Second 1.39 Second MAIN COMPUTE
7 0.38 Second 1.77 Second MAIN HOLD
8 0.15 Second 1.92 Second C GROUP COMPUTE
9 0.05 Second 1.97 Second C GROUP HOLD
-10-
CLOCK
10ms
AND
FF
o2]
COUNTER 0
RUNO 234 67 9 +R
HO 9000909009 °
| COUNTER 1
q g
REN bg 08d00606 “Bl
R COUNTER 2
RUNO 1
HO fe)
—»
—
AND
1 5
? peel
-@-
O-O O-O-
O-O 0-O-
O-O OrO
O-O O-O-
B group
C group COMPUTE
—)->—— not
| S—— COMPUTE
—p)-+)-- RESET
-il-
(1)
Other logic circuits for controlling
The logic circuit diagram indicated below is to solve a problem which has one unknown
parameter. The parameter on this diagram is continually changed during the logic
operation.
Main Operation Group
A RESET COMP
A group
B | COMP HOLD
i a — oe 7
|
|
|
I
Fig. 2.11 Logic Circuit for Parameter Change (1)
At t
A | RESET COMP
Main Operation Group OLD COMP
B H
A group
HOLD
xX
Fig. 2.12 Logic Circuit for Parameter Change (2)
The difference between the above two logic circuits is that, in Fig. 2.11, the change
interval of a is affected by the reset time of the A group; but in Fig, 2.12, the
change interval of « is decided only by the value of "k'' regardless of the reset time
of group A.
- 12 -
f
a
2.4
+
Logic circuit for analysis of boundary value equation
In most cases,
value by deciding a proper evaluating function.
observed by limiting problems to the boundary value with 1 - 2 variables.
circuits utilized in this type of equation analysis can be primarily classified into the follow-
ing three types:
(i)
(ii)
(iii)
Repetitive operation utilizing track hold
Repetitive operation
Repetitive operation utilizing a primary delay network.
a multi-boundary value equation is permited to the extreme
Thus, in this chapter, the logic circuit is
The logic
These three methods have both individual features and faults; therefore, the appro-
priate method should be applied after grasping a description of the equation.
The following logic circuits have been devised in order to analyze an unknown parameter
automatically in such a manner that the boundary condition "y = y," is satisfied when t+ t::
At ti
A group | RESET COMP
yt .
Main Computing ia B group | HOLD RESET
Group —y 1
C group | COMP HOLD
A group
tan Geenetneeite (eetreeneeteeeeee + B group
1 '
| : !
rN, 1 | lax
I I A
! — {| i OB
| Absolute value C group !
' generator '
bee ee EE 4
Fig. 2.14 Logic Circuit for Analysis of Boundary Value Equation (1)
In Fig. 2.14, integrator I, of the track hold is used for the memory element. Accord-
ingly, the time constant of integrator I, must be sufficiently smaller in comparison to that
of the main computing group.
yt , ti te ts
Main computing 1p A group | RESET COMP | HOLD
group . _y 1 '
A group B group | HOLD HOLD | COMP
5
WE KI FR-O—
' Absolute value B group
generator
Fig, 2.16 Logic Circuit for Analysis of Boundary Value Equation (2)
-13-
I
The features of this system are that no errors are made because the time constant of
the memory circuit does not affect the system (in Fig. 2.14, the time constant affects
operation), and that the number of mode sharing grouo of integrators can be minimized.
Among these three types of logic circuits, the third one can obtain the converged value of a
with minimum error.
At ti
Main Computing _
Group y A group | RESET COMP
A
aie B group | COMP | HOLD
| (0.1~0.2
a | / C | bs ( )
Absolute Value B group | P
Generator |
LoL _—_—_l
Fig. 2.17 Logic Circuit for Analysis of Boundary Value Equation (3)
* 10 indicates that the integrating
. . 1 100
time constant is 10. omne)
RT RO
O
10 1000
\
In this system, reset trangent voltage of integrator I, is integrated by integrator I,
in the B group, and the parameter @ is corrected. Integrator I. corrects and integrates a
value in proportional to the tolerance y-y;. Both the COMP and RESET time constants of
integrator I, are 0.01 second.
In comparison with Fig. 2.14, this circuit can be applied even in the time constant of
y is considerably smaller.
The scope of application of those three circuit systems explained above differs individ-
ually, depending on the wave forms of the planned ''y'"'". Moreover, in Figs. 2.14 and 2.17,
because of repetitive operation controlled by the timers, sufficient consideration must also
be given to the time-setting error of the timer. Calibration for the setting time of the timer
with an oscilloscope or synchroscope is recommended) in the case of a 2-point boundary
value question in which two unknown parameters are involved, analysis is still possible by
connecting two of the above-described logic circuits in parallel with one main computing
circuit group. However, no mutual relation is given to those two parameters, and they are
independently controlled. Thus, the tendency is that considerably excessive time is spent in
comparison with the steepest descent method described in the following paragraph. In
addition, when the number of unknown parameters is three or more, it becomes extremely
difficult to approximate. Consequently, in this case, it is better to obtain a proper evaluat-
ing function and to permute to an extreme value equation, The method of permutation is
described in the next paragraph. :
Main Computing Circuit _
x Group y
a) & op
gs A group S&
Bround gf 3 gES
roundary we Oo & <2 | Boundary conditions
conditions of “x”| «8-3 B aSs! of “y”
: a
Fig. 2.18 Logic Circuit for Analysis of‘Double Boundary Value Equation
-14-
z
iH
t
2.5 Logic circuit for analysis of extreme value equation
Ordinarily, the logic circuit used in obtaining an extreme value of evaluating function
"F" for an unknown parameter is more complicated than that for the boundary value equa-
tion. Fig. 2.19 indicates the principle of analysis when the number of unknown parameters
is one,
First of all, evaluating function ''F" (an) F(a)
pertaining to any desirable value "an" of "a"
is obtained and memorized once through the
ist trial. Next, evaluating function F (an + Aa)
pertaining to an+ Aa is obtained, and this
function is compared with the previously F(a,+ da)
memorized function F (an). F(a,)
When F (an + Sa) - F (an) 70, the value of a "
is corrected to the direction in which the value
is reduced from the trial value an through the
1st trial in proportional to | F(an+ Aa) - F(an),
and when F (an+Az) - F (an) <0, the value of Flam) Aa
a is corrected to the direction in which the —-| Le —
value is increased from en in proportional to Ge x a
[F (an+ Aa) ~ F (an). .
When the value of corrected ais an+ 1, the Fig. 2.19 Extreme Value Equation
above operation is repeated during the 2nd Analysis Principle
trial, using an+ 1 as the starting point. In
this manner, the converged value am is obtained. However, it should be noted that the
value of « may vibrate when the value of a enters the range of em+Aa, In this case, itis
recommended to reduce the value of 4aslightly at the final step of convergence.
F(a) Memory pnit.
Main computing] jt 7
groupt——o> B group|
A group F(a+Aa)
O or Ad 121 va + Comparison
( > O [ a |
Sommer
peer eee
a Correcting unit
C group
|
I
!
|
!
Fig. 2.20 Principle Diagram of Extreme Value Equation Analysis
Main computing
group
A group
F(a)— F(a+ Ae)
OFF 0.1~0.2
a 1 Ct’
cor IN VY
—(atAa)
D group
Fig. 2.21 Logic Circuit for Extreme Value Equation Analysis (1)
-15-
ty te ts ti te ts
A group RESET COMP HOLD RESET COMP HOLD
B group HOLD RESET HOLD HOLD HOLD HOLD
C group HOLD HOLD HOLD HOLD RESET HOLD
D group COM P HOLD HOLD HOLD HOLD HOLD
Relay K ON ON ON OFF OFF OFF
Fig. 2.22 Logic Control Modes
Fig. 2.21 is a circuit diagram of the flow chart shown in Fig. 2.20 expressed more
practically. The control mode is shown in Fig. 2,22. For relay K used in this circuit
is of a comparator which is driven by the flip-flop output of the logic patch board. Individual
integrators of the B, C, and D groups are directly controlled from the logic patch board as
shown in Fig. 2.25. The practical connecting method on the patch board is shown in Fig. 2.23,
Mode Control Unit (MC-151) Logic Patch Board
[Ring counter |
| RC-151A ,
IN OUTSJL OUTS { |
Rm _. O- O O | | oe
Sy | Io Flip-flop 7
c jMODE CONT! — | FF-151A |
P | OUT |
H R t |
D a
Li ee
|
i}
|
{
i
! |
= | |
RUN OUTIL OUTS l | Mode matrix
1O--O--O* | MM-151A |
2C)---+C}- Analog Patch Board 7
c “Integrator Comparator 7
IN-151 CP-151
Fig. 2.23 Control Mode Con-
nection Diagram
Fig. 2.24
Note: Terminal RS of No. 12 on the mode matrix (MM-151A) is interconnected to R of MM of
the integrator (IN-151) No. 12.
-~16-
Comparator CP-151
Comparator CP-151
| RY
t———- To R at RY of B group integrator
+——— From MODE CONTROL COMPUTE OUTPUT (C of MC of integrator
To R at RY of C group integrator
-——— To C at RY of D group integrator
+
i or mode contro] panel (MC-151) CP OUT)
im
C [———~ From MODE CONTROL RESET OUTPUT (R of MC of integrator
or mode control pane] MC-151 RS OUT)
RESET INPUT RESET OUTPUT
|
merar [TO FOEDGLO
IN-151 MM RY MC
0 |.9 |.Q@ O
\
COMPUTE COMPUTE OUTPUT
INPUT
Fig. 2.25 3B, C, and D Group Operation Control
-~17-
For all methods to resolve the extreme value described above, the number of unknown
parameters is one. Also, in the case of a multiple number of unknown parameters, the
basic idea is the same. For example, consider a case in which two unknown parameters are
involved. Assuming that the two variables are a and/, and that the evaluating function de-
cided by the variations is F (a and), upon obtaining the most suitable values (am and /m)
after starting from points ( @) and f) ), the minor change AF of F against the minor changes
of AaandAf is expressed by the following equation:
oF aF
F 75g ft + op OF
Thus, the evaluations againstAa
and A¥ are determined as follows:
ar or
(A@)o = -K5z (AF)o = “Kae
and@,and/, are decided so that the
following equations are satisfied:
@,=a,g t+ (AG),
A, =8o+ AF)a
When this calculation is performed by
an analogue computer, the evaluating
function F (a, andf, ) against the pre- Fig. 2.26 Parameter Plane
sent (a, and #, ) is obtained. Thus,
the following equations can be obtained by measuring points (ax and #, ) which are extremely
near to ( 4, and #) and the evaluating functions F (ax and, ) and F ( @o and fx) at (% and/x ):
F( 4x, )-F( 40 fo ) (OF
dyad, =(F=) ao » Bo
F (40> fx) -F( 405 fo) (2)
Pane oz
a , Bo
ax—QA,=Aa
where, { ° }
Bx-ho =AP
Position of ( 4, ; 4, ) which are much nearer to the most suitable points than (a, , £, ) are
determined as follows:
oF oF
a, =a, — kK(=—) ao » Bo B, =ho —k( ae te > Bo
This method is called the Steepest Descent method.
"K" is a positive constant, and the value may be set freely. Ordinarily, however, it is better
to take a large value as much as possible since the approximating speeds of « and # are
increased or decreased by the value size, and to increase the approximating speed. If this
value is excessively large, vibration may occur at a point near the most suitable point; thus,
ordinarily, the value of ''K" is reduced as the (a , &) approaches the most suitable point.
Now, considering an equation in which a 2-variable high-dimension algebraic equation
is solved within the range of a real quantity based on the above-described theories for the
example, let us attempt to compose a logic circuit of the analogue computer.
Assuming the given equations to be:
G (x, y) = 0 H(x, y) = 0
and the evaluating function to be:
F=|G(x, y)|+|H x y)|
-18-
the logic circuit to obtain the values of x and y so that F becomes zero can be illustrated as
follows.
Xo
F(x, + Ax,y)— F(x.¥o)
K, . Comparison I, IC 1,
—oo Constant Limited
time time
tO 0 integration x | integration
F(x,,Yo) K, CP, ; C group B group
we, Memory ak
; F(x,+ 4x,,y,) Kox
D group Yo
F(x,,.y+ Ay) — F(x0,¥0)
K, | Comparison I, Ic |,
|_ > | Constant Limited
t i time
oo— integratio K | integration
K, \ CP, C group F
a
F(x0,¥0+ Ay) Koy
Addition ,
K
F(x,,¥o) or F(x, + Ax,y,)or F(x,,yt4y)} Main Computing |
Group
F(x,y) . | Ay
Addition
A group oo
Al «]
Fig. 2.27 Extreme Value Equation Analysis Block Diagram
by the Steepest Descent Method
First of all, with both relay contacts K, and Ke set to OFF, the 1st starting points
(x, y)} are applied to the main computing group through summers Al and A2 (the values of
x» and y. may be set arbitrarily. In the main computing group, F (x, y) is prepared, and
the value is memorized once in the memory element of the D group. Next, relay contact
K, is set to ON, x,+ y, y. are applied to the main computing unit in lieu of the x+y, and
F (x) + X, yo) is obtained at the output.
The relay Ki has been set to ON; thus, the previously memorized F (x9* yo) and the F(x.+x,yo)
are applied to the comparing element CP, simultaneously, and the differential is integrated
by limited time integrator 1, of C group. Asa result, the following voltage is induced on the
limited time integrator I, of the C group: °
F
(25)
9x xo>+ Yo
Next, when K; is set to OFF, and simultaneously K, is set to ON, K (9F/@y),, .y, is induced
on the limited time integrator I, of the C group.
Now, voltages K (9F/@x)x,.y, and K ( OF/A y) x, .yo induced on the I, and I; are integr-
ated by Is and I. respectively, and x, + K (9F/@x),,.y,and yo + K (@F/ay)x,.y, respectively
are obtained at the outputs. These values must be closer to the optimized values than x “yo
described previously.
When the above operations are repeated, based on the equations in the following calcula-
tions, the values of x and y are approximated gradually to the optimized values x,, and yy.
OF.
Xo + K( 3x) x0, Yo
x1
CG]
Yi: = Yor K(3E) x , Yo
~19-
However, when the dimension of an algebraic equation becomes high, the quantity of
roots which satisfy the equation naturally becomes multiple. For this reason, the approxim-
ating values of x and y vary, depending on how the initial xo and yo are given. Thus, if those
roots are needed, the vicinity of figures where the roots are assumed to exist must be com-
pletely sought for.
y
Now, when Fig. 2.27 is composed ina
Lm
practical logic circuit, it becomes as shown LEZ a
in Fig. 2.29.
In this, the A group -- the main com-
puting group of Fig. 2.27 -- does not include
an integrator because the algebraic equation
is taken as the example. Thus, it may be
considered that the main computing group /
constantly performs the calculation regard-
less of the reset, compute, and hold.
Fig. 2.28 Parameter plane
\
+1 :
oo Kl Ax
K X —O-—e1
i0| ;
Q —x ] > xor x+Ax
A group | Main computing
group
| 1G1+1H1
I, 1 +
or
‘A group y y Toy
° K? Ay
+1 —
Fig, 2.29 Logic Circuit for Analysis of Extreme Value Equation
Operation is started with the
Ring counter output 1 2 3 0 we
A group COMP |HOLD | HOLD |HOLD entire integrators I, through Ts set
B group HOLD |RESET| COMP|HOLD to RESET, and by depressing the
C group HOLD |RESET| HOLD |COMP RUN push button on the logic control
D group HOLD |COMP | HOLD |HOLD panel, the ring counter (in which a
Relay K, OFF OFF ON OFF ne counter ene of nan an
itions is made) moves as l, 2, 3, 0,
Relay Ke OFF {OFF | OFF {ON i, 2, 3, and 0 in accordance with the
Mode control RESET -- -- -- clock time connected to the shift
INPUTL input.
More specifically, it initially becomes as follows:
A group: RESET to COMP
B group: RESET to HOLD
C group: RESET to HOLD :
D group: RESET to HOLD
- 20 -
Integrators I, and I. of the A group start from the initial conditions xand y, and
become COMP. However, outputs of the I, and I: respectively are set stationarily on -x,
and -y, Since the outputs of the integrators I. and Is of the C group still remain zero.
Next, when the rated time is elapsed, and the ring counter moves to ring counter out-
put No. 2, outputs -x, and -y, of I: and I, are stationarily set as they are and applied to the
main computing group, and|G (xo, yo)| + |H (x, yo)| can be obtained at the outputs. When
these values are applied to integrator Is of the D group, |G (xo, yo)| - |H (x0, yo)| is induced
at the output of Is, since Is is a primarily delayed circuit with gain 1. Next, when the ring
counter output moves to No.3, x) + x, Yo is applied to the main computing group through A:
and Az, because relay Ki is set to ON as soon as the output of Is is held, and G (x +Ax, Yo)
+ H(x, + Ax, yo) can be obtained on the output. |G (x+ Ax, yo) + |H (x +Ax, yo)|
- |G (x, yo){ - [H (x0, yo)| is applied to integrator I. since relay K is set to ON and when
this is integrated for a certain time, k (@F/ Ox) x, -y, has been obtained on output of the I..
(Where, k: Constant; F = F (x, yo) = G(x, y) + H (x, y)
Next, when the ring counter output moves to No.0, k (aF/@ y) Xo.
of Is in the manner identical to the above.
yous obtained at output
Accordingly, when the ring counter output becomes No.1 again, I: and I> respectively
integrate k (9F/4x),,. yo and k (9F/4x),,. y, ,and the following are obtained at the outputs:
oF. oF
“Xi = -Xo - kK) Xo, Yo “Yi = -Yo ~ ky) Xo, Yo
When the above calculations are repeated, based on the values x andy, optimized
values x, and y, of the x and y are obtainable.
An example of a logic circuit for analysis of a 5-parameter extreme value problem is
indicated in the following diagram as an example of logic circuit for analysis of an ordinary
multi-extreme value equation. This block diagram has been composed for analysis of a
5-element, simultaneous, high-dimensional equation.
-21-
rs 7, a
F(x,y,z,u,v)
B group A group
¢—o V
+1
u .
C group l
Fig. 2.30 Logic Circuit for Analysis of 5-element,
Simultaneous, High-dimensional Algebraic
i Equation
Equations solved by this circuit diagram are as follows:
G, (x, y, Zz, u, v) = 0 Where, the evaluating function is decided as follows:
Ge (x, y,....v) = 0
F(x, y, Z, U, V) =| Gi] + [Ge] +| Gs] +]Ga] +| Gs|
Gs (x, y; Z, u, v) = 0
- 22 -
The circuit of Fig. 2. 30 is intended to obtain the values of x, y, zu, u, and v so that the
F becomes zero. The operation modes to drive this circuit are indicated in Fig. 2.31.
Computation is started by setting the LOGIC CONTROL on the logic control panel to
RUN.
Ring counter output
A group
B group
C group
Relay Ki
Relay Ke ON
Relay Ks ON
Relay Ks ON
Relay Ks ON
| |
myo Oye
Q) 0) mys
iQ) oy
qTa nyo
OQ) oy]
LQ) ayo
Sh xz] a] xn] <2
ALL
RESET
Mode control panel RESET --| --| --| --| --] --
Fig. 2.31 Operational Control Mode ~
In the logic circuit for analysis of the 5-variable, extreme value equations described
above, the main computing group may not include an integrator. When the main computing
group includes an integrator, the circuit composition somewhat differs. The following
diagram shows an example of a logic circuit for analyzing 2-variable, extreme value pro-
blem (This is not an algebraic equation).
Main computing
‘group
F(@,A8)
A group
B group
Ring counter output 1 2 3 4 5 6 7 8 0
A group R Cc H R Cc H R Cc H
B group R R Cc H H H H H H
C group H R R R R Cc H H Cc
D group Cc H H H H H H H H
Relay Ki OFF | OFF | OFF ON ON ON OFF OFF | OFF
Relay K,
Relay Ks OFF | OFF | OFF | OFF | OFF | OFF ON ON ON
Relay Ky ON
Fig. 2.32 Logic Circuit for Analysis of 2-variable, Extreme
Value Problem
~23-
2.6 Time Sharing Operation
Time sharing operation is defined as a computing system in which an electronic system
function generator is used by dividing with the time band, and elements of one unit are
utilized instead of using several same units. The circuit consists of relay elements, sample
hold element (memory element), and electronic multiplier or function generator, and the
output waveform is approximated with an echelon-shaped waveform.
x1 9——_
K +100
= F(x) }
+100
x,0——_—
—F(x,)
—F(x,)
Ic
+100 indicates that the integrating
time constant is 100.
Relay K indicates that
the relay is set to OFF.
Fig. 2.33 Time Sharing Operation Circuit Diagram.
(When a function generator)
The relay contact of Fig. 2.33 repeats ON-OFF operations with 10 c/s (100 ms).
Moreover, the relation between integrators #1 and #2 and relay K should be as follows:
Relay K ON OFF
Integrator 1 RESET | HOLD
Integrator 2 HOLD RESET
*100
X2Y2
+100
K
|
l
Xe | 91
i
| ,
1
!
!
I
i
|
+100 indicates that the integrating
time constant is 100.
Fig. 2.34 Time Sharing Operation Circuit
(When a multiplier)
The above two examples utilize elements of one unit for two units. When utilizing for
three or more units, a circuit utilizing ring counter is constructed.
QT TTT Tee ~,
x K XN Ky
NO ee
x0 —0- 0
TT TT TTP TT TT ~~
— F(x)
_ F(x:)
— F(x.)
Fig. 2-35 Time sharing operation.
Ring counter
0 1 2 9
Relay
ko ON
ki ON
Ke ON
ky ON
- 25 -
Integrator In is reset when
relay Kn is set to ON.
The integrator is held except’
when relay Kn is set to ON.
3. Exercises for Automatic Programing
3.1 Equation of boundary value
Exercise (1)
Decide value of K at the following equation so that’y’ becomes zero when't = 0, and
‘y becomes 0.5 when't'= 7 seconds:
d
Sot Ky = KF(t) F(t) = 1
Solution (1):
4] At 7 sec
0.5 i A group B Cc
(Boundary
value) B group H R
B group
C group Cc H
Fig. 3.1 Exercise (1) Block Diagram
@ Observing the movement of K, adjust the converging speed with Pot-2.
+1
1.5 sec| 7 sec| 1.5 sec
0.5 A group R Cc H
1 _ u ™ B group H H Cc
y 47 OU)
1 0.1~0.2
A group -1
1 | B group
Fig. 3.2
Exercise (1) Block Diagram
Exercise (2)
Decide the value of’a’ at the following equation so that*y”becomes 0, and ‘yr
becomes 0.5, when’t’is zero; and*y’ becomes 0.5 when't’is 10 seconds.
2
ay + ay =0
Solution (1)
dt?
Fig. 3.4 Exercise (2) Block Diagram
-~27-
At {10 sec. | At
A group | R Cc H
- y
i y > B group | H H Cc
A group A group
0.5
+1
Fig. 3.3 Exercise (2) Block Diagram
Solution (2)
At |10 sec, | At
A group R Cc H
a
10 SM
IN B group | H H Cc
10 —F lS ~yfa
A group
-1 +]
0.5 lan Yl 5fa
fa. 0. a
a 10 X\
+1 .
a a
ww
0.1~0.2
B group
Exercise (3)
eo ef) 1
re 1 K+P
4) Cy
oH
Fig. 3.5
In Fig. 3.5, decide the value of K so that the overshoot of e,’against step ei
becomes 10% of the ‘ei:
€;
Solution (1):
In this system, the response
waveform for the step input becomes
as shown by e in Fig. 3.6. Thus,
when solving this equation such a
logic circuit must be developed that
e;
1.1 ‘ei'and maximum value of’es’are e,
compared each other. Subsequently, {
the maximum value hold circuit ee
described in Fig. 2.5, will employed | Overshoot
in this logic operation. |
Fig. 3.6 Step Response
ej
A group
|
tH WN 4 CP. CP
f
C)o.2 2 PA an o— |
| { |
|
\ |
{
f
i
|
os ~~ 2IllI=Z, ~------ _
|
K
| kK, 7 1H ecmee [I —~<{[h
|
I
I 1 0.1~0.2 group
j B group L . 7
| Absolute value generator {| 8 fo7 7 TTT TTT TT TTT
| |
—1le;
At} 10 sec. | At
Fig. 3.7. Exercise (3) Block Diagram A group|R{ C H
Note: It is proper to make ‘ei’ be 0.5. ; B group|H H Cc
- 28 -
Solution (2) ;
ei
as
10°—"A group
1
0.2 “Ne
il
At | 10 sec.
[ fe |
| Q 1! I A R Cc
Fe | | 0.1~0.2
2 | Absolute value, rou i . B group B H R
| ____generator _* BTONP|
Cc Cc H
Fig. 3.8 Exercise (3) Block Diagram
Exercise (4)
Decide the values of xo = (dx/dt),-y and y = (dy/dt),-9 at the following
equations so that*x"becomes 1, and"y’becomes zero, when't’is zero; and*x” becomes
zero, and*y’becomes 1, when't is 5 seconds.
d’x d’y
dt? ~ *Y at? XY
) Solution:
When the equation satisfies the boundary conditions, the solution will become
as shown in Fig. 3.9. Therefore, assuming that x and y att = 5 are dependent to
x, and y, respectively and also assuming that there is no mutual relation between
these parameters, the block diagram becomes as shown in Fig. 3.10.
I Fig. 3.9
At 5 sec At
y A group >; group A|R Cc H
Fig. 3.10 Exercise (4) Block Diagram B| H H Cc
~29-
Exercise (5)
Decide the values of ‘a’ and’b so that ‘y'"becomes‘a,; and*y’becomes"b; when‘t’is
zero; and’y' becomes‘aj} and'y’ becomes’b; when't’is 2 in the following equation:
role d
a + 0.152 4 y>=0.4 cost
dt
Solution:
When scale conversion is applied to the given equation:
d?y [gy y)
[ee = -0.1 | - a] + 0.2 cost
-1
Fig. 3.11 Block Diagram in which Time Axis is Reduced to 1/4
When this block diagram is recomposed for automatic programming, it
becomes as follows:
“1
10 0.8 of IK
04 Y
0.4
Fig. 3.12 Exercise (5) Block Diagram
- 30 -
In this equation, the optimized values of a and b will differ depending how the
initial values of ao and bo are given, Accordingly, optimized value must be obtained
by starting from all points included in -2 Sa $2 and -2Sb#2. Actually, however,
it is sufficient to obtain such values by starting from any of several desired points
after properly deciding the lattice points on the a-b plane.
(1) After setting the question.on the patch board, the 2n
proper values of ao and bo are applied to pot 3 At | See at
and 4.
A R Cc H
(2) Confirm that the values of pot 5 and pot 6 remain
the same each other. B H H Cc
(3) After the completion of converging, change the Cc R H H
a» and b, again with pot 3 and 4, and repeat the
above operations.
Fig. 3.13 Control Signal
for Driving
Extreme Value Equation
Exercise (6)
Obtain the value of K so that the control tolerance area of eo against step input
ei becomes the minimum at the following transfer function:
1
Go = + ————_——_- - ei
p?+KP+1
Solution (1):
The control tolerance area is those portions indicated by oblique lines in Fig. 3.14.
Thus, this area is obtained by calculat-
ing the following equation:
co
f | eo - ei | dt e
ti a &o
The block diagram can be expressed as follows \
by Fig. 2.21. Moreover, Fig. 3.15 indicates
the condition in which the control tolerance area
changes, depending on the size of the value of K.
ty
Fig. 3.14 Control Tolerance
Area
3 sec |10 sec; 2 sec |3 sec|10 sec |'2 sec
A group R Cc H R Cc H
B group H R H H H H
C group H H H H R H
D group Cc H H H H H
too large ot Relay K| ON| ON| ON| OFF| OFF] OFF
- 31 -
0.1~0.5
1 ei
Kok + aK
1
_K 1 B group
2 VALE C\
Absolute value
generator AK
(3) O—1 C group
OF 0.02~0.05
“Relay K
Ralay is in OFF position
Fig. 3,16 Exercise (6) Block Diagram
(1) When the value of K approaches the optimized value (km), reduce the value of Pot 3
as much as possible. 0.02 would be suitable.
If reduced excessively, an error may occur in the optimized value.
(2) The value of obtaining K can be approximately expressed as follows when the ap-
proaching value of 1,5 is assumed to be -Kn/2:
kn 1; Kn Kn 1
—— a f+ (+ AR) § Fa(Kn + A
2 2 { 2G } g(Kn + 4K)
Solution (2):
1
10
A group
0.2
1
ANYA tf
oO 0 1 2 0.1~0.5
Absolute value generates C group . ‘“ B group . .
Relay is in OFF position.
Fig. 3.17 Exercise (6) Block Diagram
- 32 -
Exercise (7)
Solve the following equations:
| x2 + y2 - 5 =0
3x2 + x3 - y= 0
Solution:
Reforming the above equations to:
F,(x, y)=x?+y= -5
F. (x, y) = 3x? - x? - y?
apply the proper values to x and y, and obtain the values of x and y so that the
following equation is satisfied:
F (x, y) =|Fi(x, y)| +] Fi(x, y)| = 0
The method of solving an algebraic equation of this type by means of automatic pro-
gramming was already described in section 2.5, therefore, how to compose a
practical circuit is explained from here on.
As the circuit outline, it is classifiable into the following four units:
Part A: Calculates F (x, y)
Part B: Calculates F (Ax + x,y) - F(x, y)
Part C: Memorizes F(x, y)
Part D: Corrects values of x and y with values which are in proportion to
F(x, y +A y) - F(x, y)
F(x + Ax, y) - F(x, y) and F(x,y +Ay) - F(x, y)
- 33 -
K, = Ax
—1 o—( )}—0+1
For adjustmeut of 0.01
correcting gain 0.1~0.5
z
=F | > 10 —x x or x— Ax
1
| 7 i WV
1 04 |! B group A group
| 10 | | ao
| 10 |
mt ila
| Perr ! 1 ! |
PartC] "| | 10 —yl IK y or y— Ay
| C group| | A group ;
[PartB | | Yo | Ay
PartD OJ o—C)— +1
0.01
| . ~ ~ 4] 7 7 - 7 |
i 0.2 f
1 x3 _x? |
| O < >| 4 1 25 5 |
I
| 0.2 |
' t
i, i
1
; |
| 10
| 0.3 H
x: ( <E 0.5 = :
[Pata Nee _
Fig. 3.18 Exercise (7) Block Diagram
100V is assumed to be 5.
When performing automatic operation control of this block diagram, use a ring
counter and compose the control modes as shown in Fig. 3.19.
Conditional terminal number 1 2 3 4 0
Relay Ki -- -- | ON -- --
Relay Kz -- -- -