EAI 580 Analog/Hybrid Computing System — Maintenance Series: Computing Components
eit
SSO
ANALOG/HYBRID COMPUTING SYSTEM
MAINTENANCE SERIES
COMPUTING
COMPONENTS
RELATED PUBLICATIONS
est to the readers of this manual,
The table below lists other publications which may be of inter
Note that main-
Unless otherwise indicated by title or footnote, all are maintenance handbooks.
tenance handbooks directly applicable to a particular system are normally supplied with the sys-
tem,
Title Publication Number
Handbook of Analog Computation 00 800. 0001-3
Basics of Parallel Hybrid Computation 07 800. 0016-0
580 Reference Handbook 00 800. 2055-0
580 Console Components Manual 00 800. 2056-0
580 Computing Components Manual 00 800. 2057-0
580 Logic Expansion Group 00 800. 2058-0
580/680 Digital Voltmeter, Model 26. 268 00 800. 2059-0
TR20/TR48 Repetitive Operation Display Units, 00 800. 2024-1
Models 34. 034 and 34.035
NOTICE
In order to enable us to process your requests for spare parts and replacement items quickly
and efficiently, we request your conformance with the following procedure:
1. Please specify the type number and serial number of
the basic unit as well as the EAI part number and de-
scription of the part when inquiring about replacement
items such as potentiometer assemblies or cups, re-
lays, transformers, precision resistors, etc.
2. When inquiring about items as servo multipliers, re-
solvers, networks, printed circuit assemblies, etc. ,
please specify the serial numbers of the major equip-
ment with which the units are to be used, such as:
Console, Type 8811, Memory Module, Type 4. 204,
Serial No. 000, etc. If at all possible, please in-
clude the purchase order or the EAI project number
under which the equipment was originally procured.
Your cooperation in supplying the required information will speed the processing of your requests
and aid in assuring that the correct items are supplied.
It is the policy of Electronic Associates, Inc. to supply equipment patterned as closely as possi-
ble to the requirements of the individual customer. This is accomplished, without incurring the
brohibitive costs of custom design, by substituting new components, modifying standard com-
ponents, etc., wherever necessary to expedite conformance with requirements, As a result,
this instruction manual, which has been written to cover standard equipment, may not entirely
concur in its content with the equipment supplied. It is felt, however, that a technically quali-
fied person will find the manual a fully adequate guide in understanding, operating, and main-
taining the equipment actually supplied.
Electronic Associates, Inc. reserves
the right to make changes in design,
or to make additions to or improve-
ments in its product without imposing
any obligation upon itself to install
them on products previously manufac-
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ADNANCED SYSTEMS ANALYSIS AND COMPUTATION SERVICES ANALOG COMPUTERS, DIGITAL COMPUTERS/ HYBRID ANALOG. bape has
TION SYSTEMS/ TEST AND CHECK-OUT SYSTEMS/ MILITARY AND INDUSTRIAL RESEARCH AND DAEonoe SERVGESIILD ENOREEA METRIC Cao NALOG AND piaiTaL
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Bulletin
CONTENTS
SECTION 1 - LINEAR COMPONENTS
CHAPTER 1 - DUAL DC AMPLIFIER 6, 614-1
OOM COTS © 0 S200 & 6 OSS! ee 6 ale
1.2. TECHNICAL DATA ...
CONSIDERATIONS
THEORY OF OPERATION
IST PROCEDURES
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‘TS LISTS
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1-1-1
1-1-2
1-1-3
1-1-6
1-1-13
1-1-16
1-1-21
1-1-29
a7
CONTENTS (Cont)
SECTION 1 - LINEAR COMPONENTS (Continued)
3.4 THEORY OF OPERATION .......+.-+- Bn ee
3.5 CIRCUIT DESCRIPTION ..... »2 es naaeiae I, ocexe i
3.6 MAINTENANCE AND TROUBLESHOOTING ...--++0+0e+ee0eee>
APPENDIX 1 - REPLACEABLE PARTS LISTS ......-- el Feaa 5
APPENDIX 2 - DRAWINGS ............ De Eee <<, ee Eee
SECTION 2 - NON-LINEAR COMPONENTS
CHAPTER 1 - HIGH ACCURACY QUARTER-SQUARE MULTIPLIERS,
MODELS 0.7. 0146 AND 0.7. 0150
1.1 INTRODUCTION ............ ele iciess oe ain @ ales ein lela oe ceasecess
1.2 TECHNICAL DATA ........ee000- vies ietarsr visas a siviviaisisis stele ais
1.3 OPERATING CONSIDERATIONS ..........ccececeees sive wieis aie =
1,4 THEORY OF OPERATION sccvnics ccc deudecsseccecescceeccece
1.5 CIRCUIT DESCRIPTION .........cccccceses Risisie stella aisles as sels
1.6 MULTIPLIER ADJUSTMENT PROCEDURE ...................
APPENDIX 1 - REPLACEABLE PARTS LISTS ..............ececcceeeee
APPENDIX 2 - DRAWINGS ..... oS oe iehee oe tate ae Sosa csiepsie's rien? sie weiaie ai
CHAPTER 2 - MULTIPLIER, MODEL 0.7, 0148
2.1 GENERAL DESCRIPTION ............00.e00000-5., ae
2.2 TECHNICAL DATA ............ Sree rete dal 2B.
2.3 OPERATING CONSIDERATIONS ...........,
Se Oe 0 C646 walk eo
2.4 CIRCUIT DESCRIPTION ....................
2.5 MAINTENANCE ........... ;
APPENDIX 1 - REPLACEABLE PARTS LISTS
APPENDIX 2 - DRAWINGS SE SNE PAS PTS CdS 6 9 ew e.8 Ben
Page
1-3-3
1-3-6
1-3-7
1-3-9
1-3-19
2-1-1
2-1-3
2-1-3
2-1-5
2-1-7
2-1-9
2-1-15
2-1-25
CONTENTS (Cont)
‘TION 2 - NON-LINEAR COMPONENTS (Continued)
CHAPTER 3 - QUAD LOG X DFG, MODEL 0. 16, 0355
3,1 INTRODUCTION ...--ececseceeeeceeeeeeeeereeeeeeeeeeeeees
3.2 TECHNICAL DATA ....-eeeeeeereeeeeeceescseeeeeeeeereeens
4.3 OPERATING CONSIDERATIONS MY tae 8 sien od nxvere Sides
3.4 THEORY OF OPERATION oe SO eae re beret io
NANCE AND TEST PROCEDURES ........0.0.000000%
ees CASTS oo San5s sae ee aaa
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see e ee eee eee ees eeseeeseeeeeseseseeesseeeoeeee
DFG TRAY, MODEL 0. 16. 0360
-weecececec ers seesreeeseesseseseeeseeeeeeeee
1
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Ol DS yee e nis asi aed nie cities aipnie Binic ap 0 4/4
= i | ae, eee 1
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Page
2-3-1
2-3-2
2-3-2
2-3-2
2-3-4
2-3-8
2-3-9
2-3-13
CONTENTS (Cont)
SECTION 2 - NON-LINEAR COMPONENTS (Continued)
9.6 TROUBLESHOOTING
CHAPTER 6 ~ POTENTIOMETER-LIMITER TRAY, MODEL 0, 42. 0342
2-6-1
6,1 INTRODUCTION ree ene gia pugiesecw Ale le dO Oe Ret eee aDer Ce ee @ 2c are 2
6.3 THEORY OF OPERATION .....ccevecccccccsveveceereeseerress 2-6-2
6.4 MAINTENANCE seeee Coe veveseesesnsseoeveeveoscesveuvweeeeneesnee 2-6-3
APPENDIX 1 ~- REPLACEABLE PARTS LISTS .....seeeeeeeeeeeess specee 2-6-5
APPENDIX 2 - DRAWINGS eee ene 2 eee eee eee eww eee 2-6-9
SECTION 3 - LOGIC INTERFACE
CHAPTER 1 - POTENTIOMETER-COMPARATOR-FUNCTION RELAY TRAY,
MODEL 0, 42, 0340
1,1 INTRODUCTION cescccccscsccccnseveencvccces Cunt On Cee 3-1-1
1.2 SPECIFICATIONS ..s.vececess A AESSPINISBLORASIS tee: Siem over eve
1.3 OPERATING CONSIDERATIONS ..,.. P0eeeeeeeseeenetertecene. 3-1-3
1.4 THEORY OF OPERATION ...seiicsnsvsvvccesice
1.8 MAINTENANCE BLESSES SLED SEES GiS| #91858) B90 BRE fe a508 oll sia ele 0-0. g=1-8
LESHOOTING ©0010 0 9100 8 0010 & 010 6 Oe ow
16 TROUB CEOS CW 0 26:8 Oa ele 6 016 S=1=9
APPENDIX 1 - REPLACEABLE PARTS LISTS
APPENDIX 2 - DRAWINGS ......
CHAPTER 2 - POTENTIOMETER, TRACK/STORE AND p
TRAY, MODEL 0, 42. 0341 /A SWITCH
2.1 INTRODUCTION
2,2 TECHNICAL DATA ..........
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E PARTS LISTS ............ ovesscscesose
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ILLUSTRATIONS
mts Title
1.1 Dual DC Amplifier, Model 0.6.0614-1 oi... cece cece ccencevenes 1-1-1
f2 Location of Dial DC AMPplifieYS vivecccccccccccccnceeeecnccees 1-1-2
| 1.3 Amplifier Patching, Typical Configuration .....ccceccccscusees 1-1-5
1.4 0.6. 0614-1 Amplifier, Block Diagram .........4. oo L-1<7
1.5 0.6.0615 Amplifier Card, Simplified Schematic .........000000- 1-1-9
‘Le Frequency Response Test Circuit ......ceseeene Sr hn ee 1-1-13
L7 Test Circuit for Measuring Noise .....00..0eceecceecenseecee I-L-14
LB Ouput Current Pest Circuit eee iee te ceeeee re 1-41-15
| re a tems ptt-te
PUEOPTIES) Oiiak aca aivln dik ee aeiliee oa 1-128
“Model 0.6.0704-2 ..eeceesesesecevenenenee 1-2-1
A pli ers Ce 1-2-2
(bee eee L-3-1
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Figure
Number
LS
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4.1
4,2
4,3
4,4
4,5
4.6
4.8
4.9
4.10
ILLUSTRATIONS (Cont)
Title
DFG Negative Synaring Adjustment Circuit sss selsas Sieadsivic 4 *
O. 7.0148 Multiplier .........ccccneceaeeeeres iat :
Multiplier Patching .ececcecccee gielnios¢ # wieie suevalienn =.209 Roliicleléesisie oie
Multiplier, Simplified Scheinatie ..... SE oc OG HO BCH CES
Error Test ..... ‘ Sails ayoste| os ouayenas <lersirene avansyare sieislsiisivere te ee ewes
Multiplier Adjustment ...... sugle Wiel arvieis alaleis aleteie rele (eleuexe: sieve asic ©
Quad Log X DFG, Model 0.16.0355 ....+.. ME ADO FON Biers CONIC
Location of 0.16.0355 Quad Log X DFG Trays ...eeseee eieeteastee
Log X DFG Patening, « «sixes ssien ts owen SD 09 Gaze eng eac o8 Sococe ae
Positive Input Log X DFG Circuit, Simplified Schematic .......
Graphical Input-to-Output Comparison of Positive Input Log X DFG
Log X DFG Dynamic Error Test Circuit .........
Log X Adjustment Location and Test Setup Patching
Location of the Sine-Cosine Tray, Model 0.16. 0360
a
Sine-Cosine Tray, Model 0.16,0360 .........
BUS S'S © (G0 ©, 0x00 sia oe
Sine- Cosine Generator Patching for Sine Function Generation
from =90° £0 490° oeces cars 09 HSN Se ial erg sea Siimee mele = WAY aco « «
Sine-Cosine Generator gers for Sine Function Generation
from -180° to +180° AW cielo: ealains's © ASI 5 « one ¢
Sine- -Cosine | Generator Palle for = Cosine Fun
from -180° to +180" ......... ction Generation
Sine-Cosine Generator Patching for - Cosine Function ;
from -180° to +180° .......0005. dae Generation
oe ee
PESTS Oe S Side weve
tee
Sinusoidal DFG Circuit, Simplified Schematic
Sine Generator Waveforms ...........
Cosine Generator Waveforms .........,
Sine-Cosine Generalor Waveshaping Circuit
2-3-7
2-4-]
2-4-2
ILLUSTRATIONS (Cont)
Number Title Page
4,11 Sine-Cosine DFG Adjustment Civ Cutt ceccsscccccscecevacs 2-4-14
4,12 AdpBENCH LOGGHOUB vp svcc ccc cesecrccsccevessescsvess 2-4-15
4,13 Operational Test Circuit sesevesccseccsccccusceeneees 2-4-17
Mperational Test WAVEfOVYMS .iessceresseccescscrcuevee 2-418
jor MDFG COmpONCHS «ees eeeeeseveecerceeseceeens 2-f-2
Out pui “it ahead Simplified Schematic 2-5-7
LT
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Figure
Number
2.2
2.8
2.4
ILLUSTRATIONS (Cont)
Title
Typical Function Relay Patching .....+++ - ay pain # altace gan noes f
Comparator, Simplified Schematic .....++ caleaeccceeereeenes
Function Relay, Simplified Schematic ..sseeeceeseererseerere?
Comparator Adjustment Circuit .iccccceceveeee® Pe trenesawes
Comparator Adjustment Controls .cecesceveecees Viale bt eee erere & >
Patch Panel Layout Showing Track/Store - D/A Switch Tray
ULOOGLIONS isneles aunige sos tee ds duoraaieie & ob acolelelolele ek eo albr elncaiele
LEW ACE RRA RIO CERT Te)(Sloso. omer sca Reeders DSSS oe meie W eres pisiate
Drack/Store Patching (PYpical) vecsacciedecs caweis aes + 5 5
D/A Switch Patching (Typcial) .iccccsecccccccvces ie anoles wi ote
Track/Store Circuit, Simplified Schematic .......cccccccecces
D/A Switch, Simplified Schematic ....... w.elsials Siena, wise aR oe F
D/A Switch Adjustinent Circuit ........ so siataialeislereielavals.¢ ‘iid Sum iore, ¢
D/A Switch Card Showing Adjustments ......c..ecc000. ase
Page
SECTION 1
LINEAR COMPONENTS
CHAPTER 1
DUAL DC AMPLIFIER 6. 614-1
1.1 INTRODUCTION
The Dual DC Amplifier Tray, Model 6. 614-1 (Figure 1.1) is installed in the positions shown in
Figure 1.2. The tray contains two etched-circuit boards; one contains two independent high-gain
amplifiers, the other contains two independent precision resistor networks which provide input
and feedback components for the two amplifiers. These amplifiers are transistorized and de-
signed for optimum stability and frequency response. Each amplifier may be used in conjunc-
tion with its provided network to perform linear computations such as summation, integration,
and multiplication by a constant. Accessory components allow use of the amplifier for operations
such as multiplication and division of variables and the generation of analytic or arbitrary func-
tions.
AMPLIFIER CARD 6.615 AMPLIFIER NETWORK 12.898
Figure 1.1. Dual DC Amplifier, Model 0.6.0614-1
1-1-1
R 6, 614-1
CHAPTER 1 DUAL DC AMPLIFIE
—
one roy aie ATTEN
Ado ATTEN | AO2 Ao® | arreNn ATTEN | Al2
¢ PAO e PIS-
Poo- 0 pio | At
ok] POS~ N Pia
Po4 POS T Pi4
R Seale
Ame | INT |-~——l amex | mucr fawpn |-—--1 © Tamer | int [eon —| AMPE | MUCT “sis _
COMP. | Ao4 oe sinew (nae 9 | 0/A
Aor Fr | aos woo | ova | Das F/R | AIS ts
ATTEN
Aad ATTEN | Az2 age |arren| | 430 ATTEN | A32 ASB fie
P20- | a23 p2s~ R P30~- | ASS
P39
P24 P29 i‘ p34 --
AMPL | int |-—--lamec | mutt } amen |----| « Pawen | int |---|] AMPe | MULT | MPL
Be Bis ] COMP | A24 Wl TS s ii i comp, | A34 p T/s
b BBE F/R | A258 D/A BS F/R | ASS ASS | 0/A
ATTEN | A42 | quad TTEN Ce ATTEN | 452 | QUAD | AS@ JATTEN
P40- | Aa3 LOG P45- ul PS5O- | ASS
Pag DFG 1 P4 U P54
INT | ——~-=-] AMPL | —-—~ won N INT J=-—=]| AMPL
MOFG k
comp | Aaa | ase /s 8 comp. | A54
F/R | A4S | Aa7 D/A F/R A55
ATTEN| AG2 | SINE/ Tren, | ATTEN | A72
P60-| A63 |COSINE r6s-| P70- | A73
P64 P69 ui P74
INT [--——] AMPL |—--— --}| N INT [=———| AMPL
MDFG K
COMP] A64 | A6e Jumiren} © comp. | aT4
F/R | AGS | AG7 i F/R A75
Figure 1.2. Location of Dual DC Amplifiers
1.2 TECHNICAL DATA
The following specifications refer to the complete 6. 614-1 Dual DC Amplifier when operated in
the computer.
Offset
Unity-Gain Inverter .....sssccesccecservcvscesseseccs 20 Microvolts, Maximum
Noise
Pel) Bandwidth... «sss ssevsnnyaeetuer: Wey, Jee
1 ‘+ 1.5 Microvolts, Peak-to-Peak
Low Frequency Gain
10 Hz aig wa BERR felieeie. (0. & & FOS SSN NCIS © & #515 ae SNe erate eee 86 db
100 Hz COTE MOIS I GE ICS SNES SUS BLINN GSO VS ern egy = 80 db
IOGO BS: Gpovetsnintien sess 2hsanethoninonliaed van gattle emi ge
Frequency Response (3 db) for Unit Gain Inverter
With 10k LATTA T RG T gee RRR ciaps I TYON oar SN Ms
400
With 100k CELE TREE WHY 90 OEE TOS SIAee Cieiplbiee aly g gicly kHz, Minimum
1-1-2
CHAPTER 1 DUAL DC AMPLIFIER 6. 614-1
1.3 OPERATING CONSIDERATIONS
The data in this paragraph is general operating information. The maintenance personnel should
be familiar with this material to assist in rapidly isolating amplifier troubles and to eliminate
causes of apparent faults due to improper amplifier usage.
1.3.1 Amplifier Balancing
The amplifiers should be periodically balanced to assure computer accuracy. Under normal
circumstances, the amplifier will remain balanced for periods of weeks. However, at intervals
it is desirable to check this condition, and if an amplifier is found to be unbalanced, then an ad-
justment should be made. The period between balance checks depends to a large extent on the
application of the amplifier. For uses which might be unusually sensitive to amplifier unbalance,
maintenance personnel ogee recognize the fact that most amplifier and network malfunctions
can be detected by checking amplifier balance. Consequently, it is recommended that a check of
amplifier balance be made once a week. If the check indicates that the amplifier balance is within
tolerance, no adjustment need be made.
N switch to the A BAL (balance) position.
id the Address alae buttons for the amplifier to
{eh ng Be
at Fat of aon folureag
pm eae “SE 2x
oe ee [tba
rae
ce, eee, Eee
DUAL DC AMPLIFIER 6. 614-1
CHAPTER 1
ight; after a few
lamps light;
When power is initially applied to the computer, all of the overload ee aie hen pylichine
ari
seconds all of the lamps should go out. The lamps may also momen
from set pot to some other computer mode,
1.3.2 Amplifier Patching
i d short patch cord runs
are also located in close proximity to the amplifiers for ease of patching an
or use of bottle plugs.
; i w ack/store network,
Patching, when using an amplifier in conjunction with an integrator network, tr / ‘ Hie
ibing th units.
or one of the non-linear components, is covered in the chapters describing these
ifi i j i ith a resistor
section is therefore limited to the description of an amplifier used in conjunction w
network.
Figure 1. 3a illustrates two of the more common amplifier patching SE SOE the ied
amplifier makes use of the standard 4-connector bottle plug and provides a summing aia as
shown schematically in Figure 1.3b. This configuration has two gain-of-one and two gain
ten inputs for summing, inversion, or multiplication.
-of-
The lower amplifier of Figure 1. 3a is shown patched for one gain-of-one and three gain-of-one
e lo
The simplified Schematic of the configura-
t is shown in Figure 1.3c, By connecting the RJ terminals of different amplifier resistor
ion is °
networks together, additional inputs are made available,
tenth inputs by using two, 2-connector bottle plugs,
as shown in Figure 1, 3d.
A eviously indicated, these are only two of many possible amplifier configurations,
- :
s : t point to note is that all amplifiers, whether used (assigned) or unu
por i | problem solution, must be provided with feedback, Failure t
a particu
it for an amplifier will cause that amplifier to overload 4S soon as
eircui
An im-
sed (unassigned) for
° provide a feedback
the computer is Switched
than SP.
to any mode other
The de operational amplifiers are rated for normal linear operational] Outputs of 119 volts maxi-
Thus the amplifier patching arrangements, regardless of the ap
mum.
Plication, should be such
that the output level does not exceed either plus or minus 10 volts, (Th
. © amplifiers are capable
f slightly higher linear outputs to allow for minor scaling discrepangj
of s
es.)
1-1-4
6. 614-1
CHAPTER 1 DUAL DC AMPLIFIER
ae 100k 100K
4 CONNECTOR
F r)
IN THIS AREA = LJ
Tom ee.
| OL/a]0
°0Q | O
2 O me (0) Simplified Schematic (Gain of 1 and 10)
WO we
2 CONNECTOR IFO OoO ~ 100K 10K
BOTTLE PLUGS ; .
CAN BE USED ie) O
IN THESE AREAS pr O
5 ol
0 | @
100 O
| DUAL AMPLIFIER
ao tie (c) Simplified Schematic (Gain of 0.1 and 1)
(@) Pre-Patch Panel Configuration pox
6. 614-1
DC AMPLIFIER 6.
CHAPTER 1 er
1.4 THEORY OF OPERATION
1.4.1 Basic Block Diagram
The Model 6. 614-1 Dual DC Amplifier consists of a 12.898 Dual Input Network and a 6. = :*
DC Amplifier Card. The components for one channel are shown in block diagram form oa is igure
1.4. The major components consist of the input/feedback resistors, the stabilizer senplitior, the
chopper, and the de amplifier. The circuit is arranged so that the drift-free characteristics of
an ac amplifier are used to cancel the effects of drift in the de section. The resulting circuit has
A, : ity of
excellent long-term stability, and allows the use of wideband de amplifier without the necessity
frequent manual balancing,
Inputs to the amplifier are applied through the input impedance Zin The de and low frequency
components of the signal voltage at the summing junction (SJ) cannot pass directly to the input
of the de amplifier section because of C1. Instead, they are connected through R3 to contact 9
of chopper D1. (A chopper or synchronous vibrator consists of a coil-driven vibrating reed (8)
that alternates between the contacts (9,7) on each half cycle of the coil excitation voltage.) The
chopper alternately grounds contact 9 producing a 60 Hz square wave input to the stabilizer ampli-
fier. After amplification, the resulting signal is de-modulated (or synchronously rectified) at
the second contact (7) of the chopper. The resulting signal at contact 7 is a pulsating de whose
polarity is the same as the polarity of the signal at the summing junction. The dc signal is
filtered by R6 and C2 and applied through R65 to the input to the de amplifier section. Thus dc or
very low frequency signals are amplified by the stabilizer amplifier and by the de amplifier.
The circuit from contact 9 of D1 to contact 7 is a modulated carrier-type amplifier that provides
The stabilizer is phase Sensitive; if the polarity
of the summing junction signal changes, the phase of the modulated Signal changes and the
polarity of the pulsating de output voltage changes.
high-gain de amplification with very low drift.
High frequency components of the input signal are passed by C1 to the de amplifier and are
?
amplified by the gain of the de amplifier only. The open loop gain of the amplifier thus depends
extremely high because
, At higher frequencies
is decreased but remains high enough to satisfy all expected REESE operations
One of the criteria for a high quality operational amp ‘fer is that the Output voltage be
the input voltage is zero. This zero correspondence between input and output volt one when
amplifier balance, The manual adjustment process to insure this corr 8 pci 1s called
balancing and it must be accurately made, following the Procedure describeq ee hy called
1.3.1. The amplifier would require more frequent balancing without stahitigar ub-Paragraph
compensation produced by chopper stabilization allows the amplifier to the Grit
attention.
on the frequency of the input signal. At very low frequencies, the gain is
the stabilizer amplifier is placed in series with the dc amplifier,
’ the gain
be useq for Weeks without
1-1-6
DUAL DC AMPLIFIER 6. 614-1
CHAPTER 1
PLIFIER 6. 614-1
CHAPTER 1 ada
Any component of the amplifier output voltage due to drift in the de amplifier a is vo
through the feedback impedance Ze to the summing junction of the amplifier. ae .
duced voltage has a very low frequency, it will be amplified by the sigiltizer Becton, : Ce
then applied as a drift-correction Signal to the input of the de amplifier Baga The eiepso-
ive gain of the
duced component in the output voltage is reduced by a factor equal to tne rettective e
stabilizer section.
The amplifier in the Stabilizer section has a very high gain. Since it is connected to the summing
junction, it serves as a monitor of the summing junction voltage. Under normal circumstances,
the input current of the operational amplifier is equal to the feedback current, and the summing
junction is at virtual ground. If the currents are not equal, the amplifier is not performing pro-
perly, and the summing junction departs fromvirtualground. This rise in voltage is amplified
by the stabilizer and results ina large stabilizer output signal that is used to trigger an overload
indicator which informs the user that the amplifier is not operating properly.
Since the stabilizer is a sensitive monitor of the summing junction voltage, the magnitude of its
output voltage is also an indication of the balance of the amplifier. The 580 amplifiers are
balanced accurately by connecting the stabilizer output to the voltmeter on the control panel and
adjusting the balance potentiometer until the voltmeter reads zero.
1.4.2 The DC Amplifier Section
Figure 1.5 is a simplified schematic diagram of the 6.615 Amplifier. The patch panel summing
minal of Figure 1.5. The
Q1 through R2 and Cl. The
ut
Two reverse-connected diodes (CR1 and CR2) are connected from the j
junction (B) of the operational amplifier is connected to the INPUT ter
ac components of the input signal are applied to the base of transistor
de components of the input signal are connected through R3 to the input of the Stabilizer section
nput to ground to limit
the charge of C1 should an overload occur. This feature allows the a
following an overload condition. The voltage at this point ig normall
duction point.
Transistors Qi and Q2 comprise the dc amplifier input Stage, Transistor Q2 j
s
1) providing sei
Voltage drop (app
tage, The e
, : ee oy Mitter - :
of Q2 provides a load for Q1. This configuration gives the amplifier oes ssuatanee
; 4 relatj ,
pedance. The base circuit of Q1 is completed through R1, and 7 okie ively high input im-
components form a voltage divider between -15 volts ang +15 volts Potentiometer. These
sets the optimum operating point for Q1, as indicat
common-emitter configuration with R7 (in resistor network NW
Q1 is used in the emitter-follower configuration, and uses the -bias,
volt) across the base-emitter diodes of Q2 as its operatin & vet
The balance Potentiom
ed byaz
ero Output from the Stabilizer s
eter
ection.
1-1-8
DUAL DC AMPLIFIER 6, 614-1
AMPLIFIER 6. 614-1
CHAPTER 1 DUAL DC
The high-frequency roll-off of the input stage is controlled by C3 and R4, in pore a .
increasing degenerative feedback from the collector of Q2 to the base of QI i ——
frequency. A de feedback is provided by R15 which tends to keep the collector of Q2 at the -
potential, regardless of temperature variations which affect the conductivity of Q1 and Q2. r
stabilizer output is connected through R6 and R5 to the input of Q1.
The output of Q2 is coupled to the base of Q3 through NW1-R5. Bias for Q3 is provided by
NW1-R4, NW1-R5, and R16. The feedback network consisting of R7 and C5 provides high-fre-
quency roll-off for the Q3 stage. Capacitor C4 provides correct phasing for higher frequencies.
The collector load for Q3 consists of resistors NW1-R3 and NW1-R1
Resistor NW1-R3 provides direct coupling from the output of Q3 to the base of Q4, as well as
forming a voltage divider with NW1-R1 to set the operating point for Q@4. The Q4 stage is con-
nected in the common-emitter configuration. The emitter is connected to +15 volts rather than
ground, to establish the correct operating points for Q4, Q5, Q6, and Q7. The collector load
for the stage consists of the parallel combination of NW1-R2 and R10. Capacitor C7 Provides
high-frequency degenerative feedback for this Stage, and the network consisting of C6 and R8
provides a high-frequency roll-off for Q4, and Q5,
‘The collector of Q4 is connected to the base of Q5 through a current limiting device, R17, This
device has a high positive temperature coefficient of resistance, Providing an increase in
resistance with an increase in current flow. This helps to stabilize the operation of Q5 by
limiting base drive. The Q5 stage is connected as an emitter-follower, with resistor R9 pro-
viding the emitter load resistor. Diode CR3 provides a Small forward bias for output transistor
Q7, eliminating cross-over distortion in the output stage,
The output stage consists of transistors Q6 and Q7, connected in a
configuration. This circuit arrangement provides the advantages
single-ended input. Both transistors are connected ag emitter-followers. Since el a
(PNP) conducts with a negative input and transistor Q7 (NPN) conducts with SRissiian on
of the transistors delivers current to the load regardless of input Polarity. With a in » One
both transistors conduct equally, and the voltage drop across the loag is sen. bar ° mee,
devices R18 and R19 perform a function similar to that of R17; by Providing fa eee ent limiting
resistance with an increase in current, they protect the output transistors trom €ase in
rent flow. Resistor R13 provides a dc feedback to the base of EXCessive cur_
complementary-symmetry
Peration with a
1-1-10
CHAPTER 1 DUAL DC AMPLIFIER 6, 614-1
1.4.3 The Stabilizer Section
The stabilizer section consists of a four stage Uirect-coupled amplifier (Q8, Q9, Q10, and Q11),
input and output coupling capacitors (C8 and C12 r¢ spectively), and a 60 Hz chopper (D1). The
Stabilizer pre-amplifies the de and very low frequency components of the signal appearing at the
amplifier summing junction, and applies the resulting signal as an input to the de amplifier sec-
tion.
1.4.3.1 The Stabilizer Amplifier. The stabilizer amplifier receives its input
from the summing junction through resistors R3, R11 and capacitor C8. The chopper grounds the
junction of R3 and R11 sixty times each second, making the input appear as a series of pulses be-
tween ground and the input level. These pulses are coupled through C8 to the base of transistor
Q8.
The input stage of the stabilizer consists of transistor Q8 and Q9. Transistor Q8 is connected
as an emitter-follower, and uses the base-emitter voltage drop of Q9 to provide operating volt-
age. The circuit arrangement of Q8 and Q9 is similar to the arrangement of Q1 and Q2 in the de
amplifier section, and provides a relatively high input impedance. Resistors NW2-R1 and
NW2-R11 provide bias for Q8. Capacitor C9 filters high frequency transients from the input
waveform. Resistor NW2-R2 provides emitter load for Q8 and bias for Q9. Transistors Q9,
Q10, and Q11 are connected in the common-emitter configuration, and are directly coupled
through resistors NW2-R4 and NW2-R6. Capacitor C10 provides high-frequency degeneration
for the Q11 stage, removing unwanted high frequency components from the output waveform.
Resistor NW2-R8 provides a feedback to the junction of NW2-R1 and NW2-R11, adjusting the
bias on @8 to maintain the stabilizer amplifier transistors at the correct operating point. The
network consisting of R12 and C11 provides phase correction for very low frequencies, and
filters high frequencies from the NW2-R8 feedback loop.
The stabilizer amplifier consists of an emitter-follower input stage which is non-inverting, and
three common-emitter stages which provide an overall phase shift of 540°. This would constitute
an apparent 180° phase shift, or an inversion from input to output. This cannot be tolerated by
the overall amplifier, since the de amplifier section provides a 180° phase shift. Any feedback
under these conditions would be regenerative, and the amplifier would be unusable. For this
reason, contacts 7 and 8 of the chopper demodulate the output of the stabilizer amplifier, to
peatlianpeiens sencotanminens, inion (R6 and C2) having the same polarity as the input.
e Sica NabeseitalAnieaniin tunis
1 from one set of contacts to the other at this rate.
DUAL DC AMPLIFIER 6. 614-1
CHAPTER 1
Te input (pin 9)
Figure 1.4 shows how one pole of the chopper (pin 8) alternately grounds the .
and the stabilizer Output (pin 7), The closing of contacts 8 and 9 at a 60-cyele vane its amplification
stabilizer input to appear as a series of pulses as described previously. This c i as
of very low frequencies or de levels, while isolating the amplifier operating levels “ag
use of a coupling capacitor. Contacts 8 and 7 effectively shift the phase of the end Sse i
a short RC charge or discharge time for C12 when closed, and a longer time (through R6
Open. This operation is more easily understood with the use of examples.
If the input to the Summing junction tends to go positive, the input to the stabilizer amplifier
consists of a series of positive pulses. The output waveform at the collector of Q11 then con-
sists of a series of negative going pulses, Note, however, that during the time that the input
pulse is present (Positive), the output (negative) at the junction of C12 and R6 is connected to
ground through contacts 7 and 8 of the chopper. This allows C12 to charge rapidly to the level
at the collector of Q11. The chopper arm then closes to contact 9, driving the stabilizer input
to ground,
The collector of Q11 goes from its negative level toward ground at this time, and the positive
changeis coupled through C12 and R6 to the input of the de amplifier,
of contact 7 and the arm of the chopper thus makes the apparent output
pulses which are filtered by C2 and R6 and provide a de input to the de
The de restoring action
a Series of positive
amplifier through R5,
If the input to the summing junction tends to go negative, the stabilizer input is a series of nega-
from a negative level toward
Scharge path for C12 when the
Pper break and contacts 8 and
7 close, the collector of Q11 goes negative and the change is Coupled through C12 and R6 to the
tive pulses. The output at the collector of Q11 is a series of pulses
ground. In this case, the chopper provides a short time constant di
collector of Q11 is close to ground. As contacts 8 and 9 of the cho
filter capacitor, C2.
1.4.3.3 The Stabilizer Filter. The Stabilizer oy
tput filter, ConSisting of Capacitor
C2 and resistor R6, has a time constant of three seconds, This
1 is extremely long with respect
to the stabilizer output waveform, consequently reducing the Tipple at the Junction of R6 and R5
to a negligible level.
1.4.3.4 Stabilizer Functions. The Stabilizer Perf
tions of (a) pre-amplifying de and very low frequency input Signals, ang (b) mai
amplifier summing junction at a point very close to groung Potential over Wide variations ;
amplifier balance. When the amplifier feedback loop is Closed (as a be} ns in
applied, the amplifier output should be zero volt. Any departure of
this point is coupled through the feedback resistor to the summing j
ntaining the
» 8nd no input is
ifier Output from
Uun