Hybrid Computer System Request for Proposal
a
HYBRID COMPUTER SYSTEM
REQUEST FOR PROPOSAL
JANUARY 1966
LOCKHEED MISSILES & SPACE COMPANY
HYBRID COMPUTER
ANALOG SECTION
INSTRUCTIONS TO BIDDERS
Bidders must respond to all numbered items. If Bidder wishes to take exception to
any requirement, he may do so provided he includes a section of his proposal labled
EXCEPTIONS and clearly indicates which item or items where he has taken an exception.
'
Bidders are to provide price breakdowns for all two digit numbered items in
Sections 1, 2, 3, and 4. ; . ’
Bidders are to provide their own guaranteed specifications whice are called for in
Section 5, and must provide the information on the forms provided in Section 10.
Other specification information will be considered only if the Method of Measurement
is clearly defined. It is requested that if other specification information is included,
_ that the formats in Section 10 be used where applicable.
Bidders proposals must contain a clear description of all aspects of their,computer —
systems and peripheral equipment. It is requested that where possible the descriptions
follow the outline in Sections 1 through 4.
Additional options will be considered if bidder clearly shows that there will be no
reduction in computing capability and what advantage the option would provide to
Lockheed Missiles and Space Company.
Any computing element proposed must be available for demonstration and testing under
system operating conditions at any time after receipt of proposals.
STATEMENT OF REQUIREMENTS:
Te intent of this procurement is to purchase five identical analog computer systems
containing all solid state computing components of the highest static accuracy and
best dynamic performance.
1.0 Minimum Complement of computing components for each of five analog computer systems:
1.1 Analog computer console and cabinets completely wired with all necessary
#
power supplies and operating controls.
Lelel
1.1.2
1.1.3
1.1.4
1.1.5
1.1.6
1.1.7
1.1.8
1. 1.9
1.1.10
1.1.12
1.1.12
Console shall contain an overload indicator systen.
Console shall contain an oscilloscope display system.
Console shall contain a Rate fest feature.
Console shall contain 4 temperature controlled capacitor oven.
Console shall contain a shielded analog patch bay. |
Console shall contain an Electronic Digital VoltMeter.
Console shall contain a transistor VoltMeter. ;
Console shall contain a reference voltage system. Voltage may be
any level. The reference system will be capable of being slaved
to any one of the four other consoles.
Console shall contain a reference divider system capable of local
and remote operation. Remote mode must be capable of accepting
inputs from a digital computer or an automatic set up device.
Console shall have a mode control system capable of local and remote
operation. Remote mode must be capable of accepting inputs from
any other analog computer, either one of two digital computers, or.
an automatic set up device.
Console shall contain an addressing system that can select any
computing component. Addressing system must be capable of local
and remote operation. Remote mode must be capable of accepting
address from either one of two digital compute rs or an automatic
set up device. |
Console shall contain a power supply monitor system capable of
reading all the power supplies in the analog computer system on
the EDVM, TVM or oscilloscope.
1.2 60 Integrators
1.2.1
1.2.2
Each capable of summer, integrator or high gain operation.
Each having the capability of at least six input resistors, 3
providing gains of one, and 3 providing gains of 10 when a normal
feedback resistor is used. |
1.3
1.4
1.5
1.2.3
1.2.4
1.2.5
1.2.6
21.2.7
1.2.9
1.3.1
1.3.2
1.3.3
Each having the capability of a selection of an integration time
constant of one second, one hundred milliseconds, ten milliseconds
and one millisecond, when used with a standard gain of one input
resistor. |
One third or more of the integrators should have the capability of
selecting an integration time constant of ten seconds when used
with a standard gain of one input resistor.
Each having the capability of electronic switching mode control
for Initial Condition, Hold and Operate modes.
Each having the capability of independent mode control for Initial
Condition, Hold, and Operate modes. —_
Each having the capability of holding the input network's summing
junction to zero volts in the Pot Set and Initial Condition modes.
Each having the initial condition summing junction available on the
patchboard.
Each having the capability of having the initial rate from the input
summing junction available for readout in the initial condition
and static check modes.
- 60 Summers
Each capable of summer or high gain operation.
Each having the capability of at least six input resistors,
3 providing gains of one, and 3 providing gains of 10 when a normal
feedback resistor is used.
Each having the capability of holding the input network's summing
junction to zero volts in the Pot Set mode.
240 Potentiometers
. 1.4.1
1.4.2
1.4.3
20 Potentiometers are to be three terminal manual set with a ground
connection to be made by a bottle plug.
All potentiometers except ‘the three terminal are to be servo set.
All potentiometers except the three terminal are to be “phase shift
compensated.
90 Electronic Multipliers
L561
Approximate ly one half of the multipliers should be class 2,
accepting +x and +y from low impedances source and providing a low
impedance output.
1.6
1.7
1.8
Lg
1.5.2 Approximately one forth of the multipliers should be class 3,
accepting +x and ty from a low impedance source and providing a
low impedance output, or accepting +x and +y from a low impedance
source and providing a current output. The patchboard configuration
should be such that the programmer has the option for either mode
of class 3 operation as well as providing for division and square
‘root modes. ,
1.5.3 Approximately one forth of the multipliers will normally be associated
with the Electronic Resolvers, but will be available as multipliers
as & programmer option when resolvers are not used.
6 Electronic Resolvers
1.6.1 Each resolver shall be capable of polar to rectangular conversion
of 2 two dimensional vectors.
1.6.2 Each resolver shall be capable of rectangular to polar conversion
, of a two dimensional vector.
1.6.3 Each resolver shall be capable of continuous resolution in both
the polar to rectangular and rectangular to polar modes.
24 Stored Program Dioded Function Generators
1.7.1 Each function generator shall be set by a pre-programmed device such
as a card, special board, or digital computer.
1.7.2 Each function generator shall have at least ten segments plus a
parallax adjustment.
1.7.3 Both the breakpoints and slope shall be adjustable.
. 1.7.4 Each function generator should be class 1, accepting x from a low
impedance source and providing f(x) as a low impedance output.
1.7.5 Pairs of function generators, by a programmer option, may be
combined for twenty segment operation.
30 Feedback Limiters |
1.8.1 Each limiter must be adjustable over the entire reference voltage.
range « .
1.8.2 Each limiter shall provide hard limiting for summers and integrators.
30 Comparators -
1.9.1 Each comparator will have its output and complemented output available
in the logic area. .
30 Electronic Switches
1.10.1 Each switch shall be capable of being controlled by any logic
signal in the logic area.
Aah
2.0
1.11
1.13
1.14
1.15
1.16
1.17
1.18
1.19
1.20
1.10.2 Each switch shall be capable of switching voltages over the entire
reference voltage range.
24 Relays
1.11.1 Each relay shall be double pole double throw.
1.11.2 Each relay shall be capable of being set by any logic signal in
the logic area.
15 Function Switches
1.12.1 Each function switch shall be single -pole triple throw.
200 Analog Trunks
250 Logic Units
1.14.1 A logic unit is defined as 4 gate, flip flop, one shot, each stage
of a shift register, each binary stage of a counter, etc.
1.14.2 Each logic unit will have both true and complemented outputs
available. . . .
1.14.3 The logic may be either synchronous or asynchronous, put if the
| latter, a clock must be available at the patchboard.
1.14.4 The logic board will have at least 100 trunk lines.
10 Analog Patchboards OO
1.15.1 Analog patchboards are to provide shielding for patch cords.
1,000 Analog Patching Elements : .
1.16.1 Analog patching elements are patch cords, bottle plugs and multiples.
1.16.2 All patching elements are to be shielded.
10 Logic Patchboards
500 Logic Patching Elements
1.16.1 Logic patching elements are patch cords, pottle plugs and multiples.
1 DC .to low frequency noise generator.
1 High frequency noise generator
Peripheral Equipment:
2.1
2.2
2.3
_15 Eight Channel Strip Chart Recorders
2.1.1 Must be capable of slaving with the analog computer mode control.
2.1.2 Must be capable of operating the analog computer mode control.
15 X-Y¥ Plotters
2,2.1 Each must be capable of plotting over a 10 x 15 inch range.
(2.2.2 Pen operation must be capable of being slaved to the analog
computer mode control.
2 Automatic Set up and Checkout. Devices
2.3.1 Must be capable of setting all servo set pots.
2.3.2 Must be capable of reading all computing components.
3.0
2.5 1 Logic Patchboard Storage System
2.3.3 Must be capable of activating the computer mode control.
2.3.4 Read and store all potsetting in 4 suitable form for reprogramming
the computer.
2.4 1 Analog Patchboard Storage System
| 2.4.1 Must be capable of holding all of the , analog patchboards ina
fully wired condition. .
2.5.1 Must be capable of holding all of the logic patchboards in a fully
wired condition. Can be incorporated with Item 2.4.
2.6 1 Patch Cord Storage System
2.6.1 Must be capable of holding all of the patch cords, both analog and
logic.
2.6.2 Shall be arranged in such a manner to facilitate patching either
analog or logic patchboards.
Spares and Test Equipment:
3.1 1 Test Rack
3.1.1 Capable of testing and calibrating all computing elements to.
original specifications, operating in the same system environment
as the computer system. .
3.1.2 Capable of testing and calibrating all logic elements to original |
specifications, operating in the same system environment as the
logic system.
3.1.3 Test rack may use spare computing components to implement the.
above tests.
1 Reference Divider System
LS)
PO
3.2.1 System must provide two voltages simultaneously, one to be used as
an input, the other to be used as a nulling voltage.
3.2.2 System must. be capable of dividing reference by .001% steps.
3.2.3 System must have preprogramming capability for selecting standard.
test and calibration voltages. .
3.2.4 System must be portable.
3.3. 1 Lot Spare Computing Elements
3.3.1 Shall include EDVM, power supplies, reference, amplifier networks ,
*.
and approximately one or two percent of the plug in spare components,
but at least two of each type of computing element or card.
3.4 1 Lot Spare Parts _
3.4.1 Shall include at least two each of each type of resistor, capacitor, -
diode, transistor and relay that are used in the computer system.
4.0 Options:
5.0
Kel
4.2
4,3
Ay
LS
Delete one computer console as described in Item 1.
Delete 3 eight channel recorders, 3 X-¥ plotters 4s described in Items
2.1 and 2.2
Delete 1 automatic set up and checkout device as described in Item 2.3.
Substitute a parallel entry keyboard for both the addressing and reference
divider systems. ; ,
Substitute electronic digital attenuators for all of the servo set
potentiometers.
Required Specifications:
5el
5.2
23
Drift
5.1.1 Arbitrary Electronic Function Generator
5.1.2 Electronic Multiplier
5.1.3 Electronic Sinusoid Generator
5.1.4 Integrator Amplifier
5.1.5 Summing Amplifier
5.1.6 SCI Method of Measurement
5.1.7 Format for results 10.1. ;
Error, Total
5.2.1 Electronic Multiplier
5.2.1.1 SCI Method of Measurement
5.2.1.2 Format for results 10.2.1
5.2.2 Combination Amplifier
5.2. e. 1 SCI Method of Measurement for Summing Amplifier with the ~
combination amplifier in the summing mode.
5.2.2.2 Format for results 10.2.2 —
5.2.3 Summing Amplifier
5.2.3.1 SCI Method of Measurement
5.2.3.2 Format for results 10.2.2
Frequency Response, Amplitude
5.3.1 Combination Amplifier
5 3. i. 1 SCI Method of Measurement for amplifier with the
combination amplifier in the summing mode.
5.3.2 Summing Amplifier
5.3.2.1 SCI Method of Measurement for amplifier.
5.3.3 Arbitrary Electronic Function Generator
5.3.3.1 SCI Method of Measurement
5.4
22
5.6
a7
5.3.4 Electronic Multiplier
5.3.4.1 SCI Method of Measurement
5.3.5 Electronic Sinusoid Generator
5.3.5.1 SCI Method of Measurement
5.3.6 Format for results 10.3.
Frequency Response, Phase ,
5.4.1 Combination Amplifier
5.4.1.1 SCI Method of Measurement for amplifier with the combination
amplifier in the summer mode.
5.4.2 Summing Amplifier
5.4.2.1 SCI Method of Measurement for amplifier
5.4.3 Arbitrary Electronic Function Generator
5.4.3.1 SCI Method of Measurement
5.4.4 Electronic Multipliers
5.4.4.1 SCI Method of Measurement
5.4.5 Electronic Sinusoid Generator
5.4.5.1 SCI Method of Measurement
5.4.6 Format for results 10.4.
Noise
5.5.1 Arbitrary Electronic Function Generator
5.5.2 Electronic Multiplier
5.5.3 Electronic Sinusoid Generator
5.5.4 Summing Amplifier
5.5.5 SCI Method of Measurement -
5.5.6 Format for results 10.5.
Recovery Time, Overload
5.6.1 Arbitrary Electronic Function Generator
5.6.2 Electronic Multiplier
5.6.3 Electronic Sinusoid Generator
5.6.4 Summing Amplifier
5.6.5 SCI Method of Measurement
5.6.6 Format for results 10.6.
Response, Transient
5.7-1 Arbitrary Electronic Function Generator
5.7.2 Electronic Multiplier
5.7.3 Electronic Sinusoid Generator
5.7.4 Summing Amplifier. ©
6.0
7-0
5%
a9
5.10
5.11
5-7-5 SCI Method of Measurement
5.7.6 Format for results 10.7.
Response, Transient, Under Capacitive loading
5.4.1 Summing Amplifier
5.6.2 SCI Method of Measurement
5.8.3 Format for results 10.8. -
Crosstalk, Patchboard Amplifiers
5.9.1 Method of Measurement 9.1
5.9.2 Format for results 10.9.
Output Impedance
5.10.1 Combination Amplifiers
5.10.2 Summing Amplifier .
5.10.3 Method of Measurement 9.2
5.10.4 Format for results 10.10.
Velocity Limit
5.11.1 Combination Amplifier
5.11.2 Summing Amplifier
5.11.3 Method of Measurement 9.3
5.11.4 Format for results 10.11
Computer System's Environmental Requirements:
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Bidders shall submit dimensioned drawings showing the physical size of all
consoles, cabinets and peripheral devices. Drawing will indicate the
location of airconditioning intakes and exhausts, power cords, and other
external cable requirements. .
Bidders shall submit a suggested arrangement of a computer system including
the arrangement of the peripheral equipment. .
Bidders will indicate the clearances required for maintenance access to
the computer system and the peripheral equipment.
Bidders shall submit floor loading data for the computer system.
Bidders shall submit electrical power requirements for computer’ system and
peripheral equipment.
Bidders shall submit airconditioning requirements for the computer system
and peripheral equipment. Data will include the volume and temperature
of the intake air and the temperature of the exhaust air.
Bidders shall submit any additional facility requirements for the installation
or operation of the computer systems and peripheral equipment. | ,
Successful bidder shall provide five (5) copies of maintenance procedures and
maintenance manuals for all computing components and peripheral equipment.
8.0 Inspection and Delivery
9.0.
&1
6.2
&.3
&.4
8.5
8.6
Successful bidder shall notify Lockheed Missiles and Space Company at
least two weeks in advance of a date for inspection of the computer systems
at the bidder's plant. . ;
Successful bidder shall provide space and test equipment for representatives
of Lockheed Missiles and Space Company to inspect and test the computer
system prior to shipment.
Shipment of the computer systems can be made gnly after successfully meeting
specifications. Meeting of specifications is to be determined by Lockheed
Missiles and Space Company. .
Shipment is to be F.0.B. Lockheed Missiles. and Space Company, Sunnyvale,
California. .
Bidder shall submit a delivery date based on receipt of purchase order.
Bidder shall provide a plan to compensate IMSC in the event bidder is unable
to meet his delivery date. .
Method of Measurement:
9.1
Cross Talk, Amplifier
The following circuit is recommended for measurement of amplifier cross
talk. Worse case results for any combination of amplifiers on the patch-
board should be given as the crosstalk specifications.
KR sin wt q ®o1
O 1
SIP S\ S02
a
Std Std _
load load
— —c To Q
Cross talk ratio = “92
KR
Suggested values of K is 1.0
R = Reference voltage.
A-10
9.2
9+3
Output Impedance
The following circuit is recommended for measurement of amplifier output
impedance.
3 KR sin wt jj y foL
ota
Load
sq S02
ota
Load ~O O
—L y x
e R
Output Impedance = _02 Max 1
KR - “02 Max
Where R,, is the value of the standard output load in ohms.
Suggested value of K is 1.0.
Velocity Limit
Velocity limit can be measured by the circuit shown below:
S e
Square iw 0
ve ;
Generator od a
Sta Std
Load Load -O O
rc cc =
a
Recommended value of K is 1.0. The frequency of the square wave generator
and the time scale of the oscilloscope should be adjusted to give the best
: t
resolution of the output slope.
Velocity limit = 2M
t -t
-Jeo .leo
Where t . is the time required for e_ to reach .Y KR and t. is the
Yeo fo) «leo
time required for e5 to reach .1 KR.
SCI square wave generator may be used.
10.0 Format
10.1
10.2
10.3
10.4
for Specifications
Drift
10.1.1 Arbitrary Electronic Function Generator
Microvolts/hour
% R/hour . . ‘
10.1.2 Electronic Multiplier
Microvolts/hour
$R/hour -
10.1.3 EHlectronic Sinusoid Generator
Microvolts/hour —
$R/hour
10.1.4 Integrator Amplifier
10.1.4.1 Hold Mode
Microvolts/second
=
%R/second
10.1.4.2 Operate Mode
Microvolts/second
%R/second
10.1.5 Summing Amplifier
Microvolts/hour
%R/hour
See Graphs
See Graphs
See Graphs
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10.5
10.6
10.7
10.8
10.9
- 10.10
10.12
Noise
Photo-oscillograms with y-axis calibrations in peak to peak millivolts
and as a percentage of R. SCI filter cut off frequencies.
Recovery Time, Overload
Photo-oscillograms with x-axis calibrations in time.
Response, Transient
Photo-oscillograms for K equal ‘to 0.1 and 0.8.
Response, Transient, under Capacitive loading.
Photo-oscillograms.
See Graphs.
See Graphs.
Velocity Limit .
Photo-oscillograms with the x-axis calibrated in time and the y-axis)
calibrated in percent of Re In addition, photo-oscillograms should be
marked with the velocity limit value.
LOCKHEED MISSILES AND SPACE COMPANY
HYBRID COMPUTER
INTERFACE SECTION
INDEX
1.0 Title
2.0 Purpose
3.0 General Description
4.0 Interface Philosophy
. 4,1 General .
4.2 Pure Digital Mode
4.3 Pure Analog Mode
4.4 Hybrid Mode
4.5 Control
5.0 Data Transmission
5.1 General
5.2 ADC Requirements
5.3 ADC System Specifications
5.4 DAC Requirements
5.5 DAC System Specifications
5.6 Isolation
5.7 Checkout Panel
5.8 Operational Configuration
6.0 General Purpose Logic
- 6.1 Logic Complement
6.2 Patchboard Terminations
6.3 Logic Compatibility
6.4 Synchronous Logic
7.0 Discrete Trunks
7.1 General »
7-2 Analog-Interface Trunks
7.3 Interface-Interface Trunks
8.0 Free Priority Interrupts
8.1 General
8.2 Description
9.0 Free Discretes
9.1 General
9.2 Parallel and Individual Control
9.3 One Shots
N
[-i
10.0 Functional Control
10.1 General
10.2 Digital Access Selection
10.3 Addressing An Analog Computer
10.4% Busy Status and End of Operation Interrupt
10.5 Address Selection
10.6 DVM Readout
10.7 Setting Pots
10.8 Mode Control
11.0 Cabling
Oo 11.1 General
11.2 ADC Channels
11.3 DAC Channels
‘11.4 Discrete Trunks
12.0 Installation Requirements
13.0 Documentation Requirements
14.0 | Software Requirements
T-ii
1.0
2.0
3.0
» 4.0
Title:
Lockheed Missiles and Space Company, Hybrid Computer Interface Section
Purpose: ‘
The purpose of this request for proposal (RFP) is to set forth the functional
description of an interface system to connect the digital and analog computers
defined in the following two RFP's:
@ Lockheed Missiles and Space Company Ryorid Computer, ‘Digital Section
e Lockheed Missiles and Space Company Hybrid Computer, Analog Section
General Description:
The proposed interface equipment (Figure 1) shall be installed at IMSC, Sunnyvale,
California in Building 1$1 as a linkage system petween analog and digital computers
which will be delivered during 1966.
The digital section of the hybrid computing system is described in the RFP
entitled IMSC Hybrid Computer, Digital Section. The analog section of the >
computing system is described in the RFP entitled IMSC Hybrid Computer, Analog
Section. The digital section will consist of two medium sized digital computers
or their equivalent. The analog section will consist of five analog compute rs
(with general purpose logic units) and two small digital set-up computers.
The proposed linkage equipment will be composed of two identical interface
systems denoted in Figure 1 as 'A' and 'B'. Both interface systems will be
distinct and independent of each other and capable of simultaneously operating
as part of separate hybrid computer simulations. |
‘The proposed linkage system will be flexible in that analog to digital channels
and digital to analog channels and general purpose logic not used in one inter-
face subsystem can be used in the other. Each of the two interface systems will
have capability for both high accuracy high speed data transmission, and effective
- control and monitoring of an independent hybrid simulation.
Interface Philosophy:
4.1 General
The following operational philosophies shall dictate the overall design
and construction of the Hybrid Computer interface described in this request.
4.2 Pure, Digital Mode
- The hybrid interface system shall not interfer nor restrict either of
the digital computers from operating in its normal digital mode, independent
of the interface and all other computers.
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FIGURE j
“LMSC HYBRID COMPUTER INTERFACE - FUNCTIONAL BLOCK DIAGRAM
L.3
4
4.5
Pure Analog Mode
The hybrid interface system shall not interfer nor restrict any combination
of the analog computers from operating in their normal analog mode, »
independent of the interface and all other computers.
Hybrid Mode
The hybrid interface system shall be composed of two identical, distinct,
and independent interface systems, 'A' and 'B', These interface systems
shall be constructed such that the following modes of operation can be
performed. ; .
4.4.1 . Each of the two interface systems shall be designed and constructed
such that unused analog-to-digital and digital-to-analog conve rsion
channels (ADC, PAC) and unused general purpose logic in one
interface system can be used by the other interface system
(See: 5.2.2 and 5.4.11).
4.4.2 Component failure (e.g., power supply, disconnected cable, etc.)
in one interface system shall not interfer nor restrict the
standard operation of the other interface system. (The word
‘standard’ refers to an interface system that does not utilize
unused equipment in the other interface system).
4.4.3 “Two hybrid computing systems can be mechanized and operated -
simultaneously and completely independent of one another.
4.4.4 One group of analog computers, one interface system, and one
| digital computer can be delivered to IMSC where they will be
checked out, and operated both independently and as a hybrid
computing unit. The remaining computing equipment can be assembled
and checked out at another location (e.g. vendor's factory). The
interface vendor shall state the change in cost and physical size
of the complete interface system if this operational philosophy
Chu. k) is recinded.
Control
The area of control involves all those functions of the linkage equipment
which involve the controllability of the interface system from the digital
computer, analog computer, and from the interface logic patch panel. This
request indicates what functions must be controlled, but the implementation
of these controls is a direct function of the particular analog and digital
computers and is left up to the system designer. It will be the
responsibility of the vendor to furnish a satisfactory operating system.
|
i
This document should be used only to determine the functional capabilities
and not be used as a specification for equipment design. The responsibility
for linking the equipment to the analog computer and to the digital computer |
is the responsibility of the vendor. .In evaluating the proposed system,
Lockheed will be interested in the command structure utilized by the
- digital computer in controlling the interface. The execution times of
these commands will be evaluated and must be contained in the proposal.
Every effort should be made by the vendor to implement the functional
capability of the equipment with off the shelf design and equipment.
5.0 Data Transmission System:
5.1 General
5.1.1 The transmission and processing of continuous data signals between
the analog and digital computers shall be accomplished in each of
the two interface systems by the analog-to-digital and the digital
to-analog systems. Analog computer signals shall be digitized
and sent to the digital computer via the Analog-to-Digital |
Conversion (ADC) system (Figure 2). Digital-to-analog signals
shall be processed and transmitted to the analog computer via
. the Digital-to-Analog Conversion (DAC) system (Figure 3).
5.1.2 Control of the ADC sample and hold amplifiers and the DAC output
registers shall be governed py the digital computers. However,
the system shall be designed such that the two interfaces will
have the capability to override and synchronize control by
appropriate patching of general purpose logic on the interface
; patchboards.
5.1.3 A switching arrangement shall be incorporated within the hybrid
DAC interface system to provide switching control of unused DAC
and/or ADC channels in one interface system to the other interface
system. | :
5.1.4 The discussion and description of the ADC and DAC systems that
follow, place a lower limit, not an upper limit, on the
characteristics and capabilities of the data transmission system's
components. The primary concern of this request is to obtain two
independent and flexible sets of ADC and DAC systems that can
reliably transmit data between the analog and digital computers at
‘a maximum THROUGH-PUT rate, with a maximum THROUGH-PUT accuracy
and resolution, and with a minimum amount of noise and distortion.
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DIGITAL TO ANALOG CONVERSION SYSTEM
5.2 ADC Requirements:
5.2.1 General
Each of the two ADC systems (Figure 2) shall include cabinets,
chassis, and associated power supplies wired and with all the
necessary cabling to the digital and analog computers and:
-- 5.2.2 The hybrid interface shall contain a total of 64 ADC channels --
32 with sample and hold amplifiers, 32 without sample and hold
amplifiers. The vendor is requested to supply a unit or modular
“-~" price with his proposal for ease of modification.‘ons.
5.2.3 . The ADC channels will be conre cted to the analog computers '
patchboards as shown in Figure 2. Each of the four analog computers
(Numbers 1,2,4,5) will be connected to 16 different ADC channels;
8 channels containing sample and hold amplifiers, & channels with~
out sample and hold amplifiers. :
5.2.4 All ADC channels shall accept analog voltages from the analog
patchboards that will range from plus to minus 100 volts. ‘The
vendor shall discuss a method by which his proposed ADC system
can detect analog input voltages that exceed 100 volts.
5.2.5 All ADC channels will be constructed such as not to degrade the
analog computers’ operation by excessive loading.
- 5.2.6 The two ADC systems shall be independent such that a malfunction
or power shutdown in one interface system will not affect the
standard (See: 4.4.2) operation of the other.
902.7 Interface 'A' shall contain the 32 ADC channels connected to
‘analog computers numbered 1 and 2. Interface 'B' shall contain
the remaining 32 ADC channels connected to analog computers
_ mumbered 4 and 5. ,
5.2.8 Each interface system shall be able to random and sequentially
monitor all ADC channels independently of one another. The vendor
should describe the operational modes of his proposed ADC system
: din detail. a
5.2.9 It is desirable that each of the two interfaces contain a multiplexer
and address system such that the 64 ADC channels can be expanded
up to 96 channels after delivery of the hybrid interface system.
The vendor is requested to describe the expansion capability of
his proposed ADC systems. He will include two supplementary
5.2.10
prices in his quotation: The price per additional ADC channel
with a sample and hold amplifier; the price per additional ADC
channel without a sample and hold amplifier.
The ADC resolution shall be 14 bits (13 bits plus sign) or more.
If the vendor has the capability of furnishing an ADC system(s)
with a resolution exceeding 14 bits, he should document, price
and include that system(s) as an option to the 14 bit ADC system. -
If the vendor has a preference for one ADC system over another
(e.g. resolution), he should state his preference within his
proposal and discuss his reasons.
- §.2.11 The control of the 16 sample and hold amplifiers in each of the two
ADC interface systems shall be connected to their corresponding
Interface Logic Patchboards (Figure 2) in such a way as to allow
signals from the logic patchboards to override and synchronize
sample and hold commands originating in the digital computers. The
vendor is expected to include a complete description of his
proposed sample and hold control system in his proposal. Desirable
features of this system would be: If no patching is made to a
sample and hold control hole on the logic patchboard, then the
sample and hold amplifier represented by that patchboard hole would
respond directly to sample and hold commands emanating from the
digital computer. A 'disable' signal patched into the hole would
delay execution of the digital computers' command until the signal
from the logic patchboard changed to ‘enable’.
5.2.12 An ADC sample and hold selection switch (manual) shall be included |
within the hybrid interface system by which an operator could
distribute the control of the sample and hold amplifiers between
the two digital computers. “fhe switch should functionally operate
as follows: If an operator manually positions the switch between
numbers n and ntl; Sample and hold amplifiers numbered up to and
including n would be under control of digital computer 'A',
(digital computer 'B' could monitor the output of the sample and
hold. amplifiers, but it could not control the amplifiers); sample
and hold amplifiers numbered n+1 and greater would be assigned to
digital computer 'B' (digital computer 'A' could monitor the output
I-5
of the sample and hold amplifiers, but it could not control the
amplifiers). Standard ADC system operation would be achieved
when the switch was positioned between numbers 16 and 17
| (See: 4.4.2)
5.3 ADC System Specifications
5361
5.3.2
5.3.3:
General
The manufacturer shall include the following specifications in his
description of his proposed ADC system. In these specifications
ADC THROUGH-PUT and S/H shall be defined as:
& ADC THROUGH-PUT; From the analog computer's patchboard
to the digital computer's memory.
« S/H: Semple and Hold or Track and Store amplifier.
ADC THROUGH-PUT rate 1:
This rate shall specify the speed at which 16 ADC channels
with sample and hold | amplifiers (S/H) can be sequentially addressed
and their voltages digitized and transferred to one of the digital
computer's memory storage. The ADC THROUGH-PUT rate shall be
commensurate with the THROUGH-PUT accuracy 1. The rate shall be
derived under the following conditions: |
o $/H amplifiers have previously been placed in their. hold
- (store) mode ;
e S/H amplifiers are connected to the first through the sixteenth
multiplexer channels;
-@ The multiplexer shall start with its first channel and advance
, sequentially to its sixteenth channel;
e S/H amplifiers connected to even numbered multiplexer channels.
will represent maximum analog output voltages of the opposite
. polarity as those connected to odd numbered multiplexer channels.
(e.g. Chan 1, +100V; Chan 2, -100V; Chan 3, +100V3 +003
, Chan 16 -100V).
ADC THROUGH-PUT rate 2:
This rate shall specify the speed at which the information on the
17th through the 32nd multiplexer channels (without S/H amplifiers)
can be sequentially addressed, digitized and placed in, the digital
computer's memory storage. The ADC THROUGH-PUT rate shall be
commensurate with the THROUGH-PUT accuracy 2. The rate shall be
derived under the following conditions:
5.3.4
5.3.5
5.3.6
5 +367
@ The sixteen analog input channels without S/H amplifiers shall be
connected to the 17th through the 32nd multiplexer channels;
® The voltages from the analog patchboard on the sixteen direct
lines of the multiplexer shall alternate between plus and minus
peak analog output voltages (e.g. Chan 17, +100V; Chan 18, -100V;
Chan 19, +100V; ...3; Chan 32, -JOOV).
ADC THROUGH-PUT accuracy 1:
This value shall specify the accuracy with which the ADC system can
transpose an analog voltage on the analog computer's patchboard
(via a S/H amplifier, multiplexer and ADC) into a digitized number
and store it within the digital computer's memory. ADC THROUGH-PUT
accuracy shall include errors from all contributing sources (e.g.
S/H amplifier; ADC resolution; component off-set, gain, linearity;
allowable settling times), and shall be that error which is
associated with the ADC THROUGH-PUT rate 1. The value shall be
specified as a percent of the peak analog output voltage (e.g.
10.03% of 100 volts).
ADC THROUGH-PUT accuracy 2:
Wit