580/680 Scientific Computing System — Maintenance Series: 26.268 Digital Voltmeter
Lehrstuhl! fir MeB- und Regelungstechnik
im Maschinenbau und in der Verfahrenstechnik
Technische Hochschule Karlsruhe
580/680
SCIENTIFIC COMPUTING SYSTEM
M aintenance g eries
26.268
DIGITAL VOLTMETER
NOTICE
In order to enable us to process your requests for spare parts and replacement items quickly
and efficiently, we request your conformance with the following procedure:
1. Please specify the type number and serial number of
the basic unit as well as the EAI part number and de-
scription of the part when inquiring about replacement
items such as potentiometer assemblies or cups, re-
lays, transformers, precision resistors, etc.
2. When inquiring about items as servo multipliers, re-
solvers, networks, printed circuit assemblies, etc. ,
please specify the ‘serial numbers of the major equip-
ment with which the units are to be used, such as:
Console, Type 8811, Memory Module, Type 4, 204,
Serial No, 000, etc. If at all possible, please in-
clude the purchase order or the EAI project number
under which the ooo was originally procured.
Your cooperation in supplying the required information will speed the processing of your Peqnerts
and aid in assuring that the correct items are supplied.
—_ It is the policy of Electronic Associates, Inc. to supply equipment patterned as closely as possi-
ble to the requirements of the individual customer. This is accomplished, without incurring the
prohibitive costs of custom design, by substituting new components, modifying standard com-
} ponents, etc., wherever necessary to expedite conformance with requirements. As a result,
this instruction manual, which has been written to cover standard equipment, may not entirely
concur 2 its content with the ee supplied. It is felt, however, that a technically quali-
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Bulletin No. 1L-64104-10
July, 1967
CONTENTS
CHAPTER 1 - GENERAL DESCRIPTION
1.1 INTRODUCTION ..cccceccscccccecccsssccscteenenccetsveteeeens
1,2 PHYSICAL DESCRIPTION ....-eecsscvecccscccsecesacesevcccens
1.3 TECHNICAL DATA AND SPECIFICATIONS ..ceesesescceeeseeees 1-8
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Pere eeeeeseesseoeeeoeeetsseeseseeoes 2-2
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ILLUSTRATIONS
sere
| Number Title Page
1.1 Digital Voltmeter, Model 26.268 ........cccecececceeeeeees iv
7 1.2 Model 26.268 DVM, Top View Showing Plug-In Cards .....++. 1-3
j 163 26.268 DVM Showing Fixed ComponentS ......0cceeeeeeeeees 1-4
= 1.4 DVM Rear View Showing Connectors .....ceccsesesceseneess 1-9 |
L ou DVM, Model 26.268, Block Diagram .....ceccseceseeeceees 3-2
Input Unloading Amplifiers, Simplified Schematic ........++. 3-4
and Typical Gated Resistor Matrix,
d Schematic i i oc ed 8-5
3.4 DVM Timing Diagram oe cecccccevcccccccceceeuecececeees 3-7
‘Payt 1) DVM ae Flow Diagram (Zero Set and Polarity Check)
ric Flow Diagram (1000's BCD Operation) ...
‘ic Flow Diagram (100's, 10's, and 1's BCD
ee ee ee ee
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CHAPTER 1 GENERAL DESCRIPTION
(a) Three-Quarter Front View
“CONNECTOR Jt
~ CONNECTOR J2
(0) Three-Quarter Rear View
Figure 1.1. Digital Voltmeter, Model 26, 268
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CHAPTER 1
GENERAL DESCRIPTION
1.1 INTRODUCTION
The 26. 268 Digital Voltmeter (DVM) shown in Figure 1.1, is a complete analog-to-digital con-
version unit, containing a power supply, analog input amplifiers, and all necessary logic cir-
cuits, The unit is designed and manufactured by the Instrument Division of Electronic Associ-
ates, Inc. (EAI), specifically for installation in the EAI 680 Scientific Computing System, A
separate display unit (Model 554. 048) is mounted on the computer control panel and indicates
digitally the value and polarity of any analog input voltage within its range.
The DVM range is fixed at +10 volts and has a 20% overrange capability. The display provides
a five digit readout, polarity and decimal point symbols. The display is scaled in computer
units (in the 680, one computer unit equals 10 volts), so the maximum reading with overrange
is +1.1999 computer units, equal to 411.999 volts, An input unloading network provides an
extremely high full time input impedance.
The DVM uses the programmed-comparison (successive-approximation) conversion princi-
ple that combines accuracy and high speed. The unknown input voltage is connected to a pair
of cascaded operational amplifiers that provide an unloading circuit, as well as providing both
polarities of the unknown voltage to the digitizing circuits. The logic circuits in the DVM se-
lect the necessary polarity for conversion and display the corresponding polarity symbol on
the readout unit. The DVM then compares the unknown with a precise reference potential of
the opposite polarity, added in binary-coded decimal increments, until the algebraic sum of
the unknown and the reference is equal to zero. The DVM registers then contain a binary-
coded decimal (BCD) representation of the unknown input. Decoding circuits within the DVM
provide an output to the display unit that is the decimal equivalent of the stored BCD data.
The input sampling rate is determined by the ac line frequency, so that conversions occur 50
or 60 times each second, The conversion time (without a polarity change) is fixed at approxi-
mately 2 milliseconds, and the value is displayed during the time between convert commands.
Conversion Delay Network 12,1654 delays the convert command to permit the DVM to phase lock
with ripple voltage in the 580/680 Computer. Variable resistor R3, located on the 12.1654 circuit
board, controls the amount of delay.
1.2 PHYSICAL DESCRIPTION
The DVM chassis houses the power supply and the necessary analog and logic circuits for the
digital voltmeter. Table 1.1 lists the physical characteristics of the 26,268 Chassis.
1-1
‘om
CHAPTER 1 GENERAL DESCRIPTION
— a:
Table 1.1. 26,268 Chassis Physical Description
Dimension a
Height 5-1/4 Inches
Width (With Panel) 19 Inches
Depth 16 Inches
Weight 20 Pounds | J
nput components) are
Most of the DVM components (except for some power supply and analog i
e 1.2, and shown in
These cards are listed in Tabl
mounted on plug-in etched circuit cards.
ards are shown in Figure 1.3.
Figure 1.2. The components that are not mounted on plug-in ¢
f_
Table 1.2. 26.268 DVM Plug-In Components (See Figure 1. 2)
Model LL
Component Number Quantity Connector Position
Dual DC Amplifier 6. 463-5 1 (AR2) i
Reference Amplifier 6. 736-1 1 (AR1) L-
Miscellaneous Network Card 12.937-5 1 (NW3) |
Summing Resistor Network Card 26, 116 1 (NW2)
Comparator and Diode Gate Card 26. 242 1 (A8)
BCD Counter 38. 032 3 (A1l-A3) ~
BCD Counter 38. 032-1 1 (A4)
Power Supply Regulator 43,141 1 (VR1)
Programmer 44, 302-1 1 (A5) 4
‘
The DVM is provided with three connectors at the rear (towards the front of the computer) that
provide power and signal inputs to the unit, and outputs to the display indicators, These con-
nectors are listed in Table 1,3. Tables 1. 4 and 1.5 list the pin connections for Ji and J2, re
, re-
spectively. Pin connections for J 3 are provided in Table 4.1 in Chapter 4.
\
a
Table 1.3. Connectors and Mating Plugs (See Figure 1. 4)
DVM Connector Mating Computer Connector Function
mn DV-P1 Signal Input-Deci
- imal
to Display ai
= DV-P2 Power Input-BCD Output
a None Test Connector ]
\
ll ll
CHAPTER 1
38.032~-0
BCD COUNTER
CARDS
Feet
A4
38.032-1
BCD COUNTER
CARD
AS
| 44.302-0
PROGRAMMER aaa
CARD
ers)
GENERAL DESCRIPTION
Nw2
26.116-1]
SUMMING RESISTOR
NETWORK
VRI
43.141-0
POWER SUPPLY
REGULATOR CARD
NWS
12.937-5
MISCELLANEOUS
NETWORK
A8
26.242-0
COMPARATOR
AND
DIODE GATE
ARI
6.736-0
REFERENCE
AMPLIFIER
AR2
6.463 -6
DUAL DC
AMPLIFIER
Figure 1.2. Model 26.268 DVM, Top View Showing Plug-In Cards
1-3
GENERAL DESCRIPTION
CHAPTER 1
SERIES REGULATOR
TRANSISTORS
Q1-a6
POLARITY RELAY
Kt
(51.202 NETWORK)
R13
NW4 RECTIFIER
NETWORK
12.1106 SERIES
REGULATOR
Q7
CR4
FILTER
CAPACITORS
Cci—C7
POWER
TRANSFORMER -
(TI)
R6
|
;
:
|
;
(BEHIND
{ PANEL)
(c) Three-Quarter Rear View
Figure 1.3. 26.268 DVM Showing Fixed Components
1-4
BR I I a IN MN ce MMI ce MN oe I Ie I I I I I I |
CHAPTER 1 GENERAL DESCRIPTION
] Table 1.4. Connector J1 Terminals
7 | Pin Function Electrical Characteristics
1-A | Decimal 1 (Units)
\ dep 2 -0, 8 volt* indicates presence of digit or symbol (can
a supply up to 5 ma of current), -7 volts indicates ab-
(1-C 3 sence of digit or symbol (can supply up to 1 ma of cur-
| 1-pD 4 rent).
| 1.8 5 See Drawing D026 268 0S, Sheet 3.
| 1-G 7
| 1-H | 8
1-3 9
| 1-K 0
/1-L | Decimal 1 (Tens) |
am | 2 |
GENERAL DESCRIPTION
CHAPTER 1
Table 1.4, Connector J1 Terminals (Continued)
Pin Function Electrical Characteristics
2-P 6
2-R 7
2-S 8
2-T 9
2-U 0
2-V | Decimal 1 (Ten-Thousands)
2-W 0
2-X | + Indicator
2-Y - Indicator
3-A | Decimal Point Indicator Ground | -8 Volt Ground
3-B | Readout Display Ground -8 Volt Ground
3-C | Readout Display Power -8 Volts
3-D Zero Adjust Emitters of differential comparator amplifier to
3-E Zero Adjost zero adjust pot.
3-F Zero Adjust Pot Wiper +40 volts through a 56K resistor.
3-G | Signal Ground Zero current ground reference.
3-H = Readout Feedback Resistor | Connection between pins 3-H and 3-K changes gain
of first unloading amplifier from 1.25 to 0.125,
3-5 Signal Input Analog signal from 0 to +11, 999 volts,
3-K | Unloading Amplifier 1 Summing | See connections for pin 3-H above.
Junction
Table 1.5. Connector J2 Terminals
Pin Function Electrical Characteristics
1-A | Units BCD 1 Output normally taken from th :
i ations. -12 volts (from a Eyres te ioe ao
1-B from the NOT terminals indicates ma i of 2K)
1-C 2 a bit (can supply up to 0.5 ma of curr Porc of
(from a saturated transisto ent); +2 volts
1-D 2 T source) indicates the
absence of a bit (can suppl
PPly up to 5.0 ma of cur-
1-E 4 rent). Complementary signals are avai nes
i-F q TRUE output terminals, available at the
1-G 8
1-H 8
1-3 Tens BCD1 —
1-K T
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| |
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CHAPTER 1 GENERAL DESCRIPTION
Table 1.5. Connector J2 Terminals (Continued)
Pin Function Electrical Characteristics
1-L 2
1-M 2
1-N 4
1-P a
1-R 8
1-S 8
1-T | Hundreds BCD1
1-U ic
1-V 2
1-W 2
1-xX 4
1-Y 4q
2-A 8
2-B 8
2-C | Thousands BCD* 1 *NOTE
2-D Bp The thousands % and ® bits at pins 2-F and 2-K,
2-E 3 respectively, erroneously indicate a thousands ten
ue 2 for a 10,000 or 11,000 count, The thousands 2
me i and ch bits at pins 2-M and 2-N, respectively, in-
dicate the correct BCD code.
2-H a
2-J 8
2-K 8
2-L | Ten-Thousands BCD 1
2-P T
2-M | Thousands BCD* 2
2-N ch
2-R | Conversion Complete Signal Complement of signal at pin 2-S.
Complement
2-S | Conversion Complete Signal -12 to +2 volt leading edge of pulse indicates start
of conversion; +2 to -12 volt trailing edge indicates
end of conversion.
2-U | Zero Set Signal +2 volt level with -12 volt pulse (100 microseconds
minimum duration at beginning of conversion cycle).
2-V | +Sign Flip-Flop 42 volts when input unknown is positive; -12 volts
i a when input unknown is negative.
| aeW Tie Flip-Flop Complement of signal on pin 2-V.
eo
GENERAL DESCRIPTION
CHAPTER 1
Table 1.5. Connector J2 Terminals (Continued)
Pin Function Electrical Characteristics
2-X | HOLD Signal Input External hold of conversion cycle; display remains
constant until command is removed. Input should
be a -12 to -25 volt level (normally, -15 volts),
from a source capable of delivering 1 ma of cur-
rent. See Chapter 2, Paragraph 2. 3.
2=-Y | -15 Volt Supply*
3-A | +2 Volt Supply*
3-B | External Trigger (Convert 10-12 volt positive-going pulse with a rise time
Command) <5 microseconds, and a duration of at least 20
microseconds. See Chapter 2, Paragraph 2. 3,
3-C | H-F Clock 8-10 ke "Master" clock, -11 to 0 volt pulses of 10
microseconds duration, rise time <1,5 micro-
seconds,
3-D | Internal HIGH Clock 50/60 eps line frequency clock (normal Convert
Command), -11 to 0 volt pulses, <1.5 microsec-
onds rise time, 8 milliseconds in duration at 60
cps.
3-E | H.Q. (High-Quality) Ground Zero current ground reference.
3-H | H.Q. Ground Same as above.
3-5 +10 Volt Reference Input Computer reference to DVM reference amplifier,
3-K | +15 Volt Supply*
3-L | Internal LOW Clock 1-3 cps, -12 to 0 volt pulses, 10 microseconds in
duration with a rise time of less than 1.5 micro-
seconds. See Chapter 2, Paragraph 2. 3.
3-P +Ground Common ground for all DVM power supplies.
3-U 117 VAC Common ee ee ut terminals, For operation
rom 117 vac, 50/60 cps, pins 3-W and 3-X should
3-W | 117 VAC Hot be connected to 117 vac HOT input and pins on
3-X | 117 VAC Hot and : oe be connected to 117 vac COMMON
input, For operation from 230 vac, 50/60 cps
3-¥ | 117 VAC Common pins 3-W should be connected to 230 vac HOT input
pins 3-U and 3-X should be jumpered i
: pered together, and
pin 3-Y should be connected to 230 vac COMMON
See Schematic D026 268 0S, Sheet 4, :
3-V | Chassis Ground
Power Requirements
105 to 125 VAC at 50/60 CPS, provisions for 210-
1.3 TECHNICAL DATA AND SPECIFICATIONS
250 VAC operation.
83 VA at 117 VAC 60 CPS
*See Paragraph 1.3 for voltage tolerances.
=
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-
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_
J 3 A AAA AAE Ss
a.
CHAPTER 1
GENERAL DESCRIPTION
EAI PART NUMBER 542 0990
MATING CONNECTOR PART NUMBER 542 0980
AS Connector Shell Connector Blocks Pins Sockets
signati Part Number Qty. | Part Number | Qty. | Part Number | Qty. | Part Number
: J1 198 952 0 3 54212440 |— 54 | 6741450
J1 Mating
Connector* | 198 953 0 3 54212430 | 54 674 1440 —_—
J2 198 953 0 3 542 1243 0 58 674 1440 —
J2 Mating
Connector* 198 952 0 3 54212440 | — 58 | 6741450
*Note: 2 gs shell (EAI Part No. 198 925 0) may be used with the mating connector for
gure 1.4, DVM Rear View Showing Connectors
am =
CHAPTER 1
GENERAL DESCRIPTION
69 Watts at 117 VAC 60 CPS
+10 VDC +0,01% at 1 MA; Ripple <1 MV P-P (Computer melerenoe)
Internally Generated Power Levels (At 115 VAC 60 CPS Line Voltages)
+40 VDC 41% 2. cccccccccccccccccvsscccccescssnnesereeree®
ORM REG: <5 cy aaea ccuea cbuaeeleeewesenmnencenes haneionener*
20 VDC 41% c.ccccccecccsccccccsseccccccssversvcsecsecrosss® 80 MA
+15 VDC 45% ...eeeeee nee Pmenseressaconsee 20 MA
EDS VIC 45% cies vcice's ocicieiaesss vices scces vocincscenccscesecses 300 MA
“75 VDC 27% .cccececcvccovcccsscccesceccsonsesesooesorsrs® 920 MA
HF VDCEION sewn vecccicine oedcndissinreccrceseessosssosssesee® 650 MA
=8 VDC Unregulated ..ccccsscccccccecccerscecescrscrneseree® 480 MA
-21 VDC Unregulated ...c.ssccccccncesscccsssscseererers rere” 25 MA
6.3 VAC Pe cecsee teste ee ea tetieds-secennceel, .Amperes
-100 VDC +0. 005% edsrecveeccesesereeerecoeserrree © 20 MA (Reference)
(With Respect to Computer Reference)
20 MA
35 MA
Range
0-10 Volts +20% Overrange (00. 000 to 11,999 Volts)
Input Impedance
500 Megohms Minimum at Full Scale*
Conversion and Display Time
Converts in 2 Milliseconds
Displays for 14. 7 Milliseconds (60 CPS Line Frequency)
Displays for 18 Milliseconds (50 CPS Line Frequency)
NOTE
The unknown input voltage is sampled continuously at a
rate of 50 or 60 samples per second, depending on ac
line frequency.
_ Accuracy
£0, 01% of full scale** +1 digit with respect to the DVM -100 volt reference and
+10 volt computer reference.
*Maximum input current does not
x#Pull scale is defined as 10. 000 volts.
exceed 20 nanoamperes at any input voltage within the range.
a
|
GENERAL DESCRIPTION
- Operating Temperature Range
50°F to 100°F at Rated Accuracy
40°F to 120°F Maximum Operating Range
ye in reading of 0,0005% per °F typical. (This does not incl
erature coefficient; a maximum change in reading of 0,0008%
a age the zero oe temperature may be expected, This
ng from the zero set temperatur
ing te Eo AO control.) pe e may be eliminated, however,
}
CHAPTER
4 LJ saat all ati
_ =
's
CHAPTER 2
INSTALLATION AND OPERATION
2,1 INSTALLATION
The DVM and the display unit are installed in the computer before shipment. The DVM is com-
pletely adjusted and calibrated prior to shipment, and should be ready for use when received.
The DVM should be checked as a part of the general visual inspection when the computer is re-
ceived, to assure that all connectors are in place and that none of the etched circuit cards have
been jarred loose.
Avid Preliminary Checks
When visual observations confirm that all etched-circuit cards and the connectors in J1 and J2
are properly installed, a check of the electrical operation may be performed,
1. Check that all required power levels are present; initially, this may be
performed with any 10% accuracy voltmeter. The voltages are present
at J3 on the rear of the DVM chassis, Refer to Table 4.1 in Chapter 4 to
locate the appropriate pins.
2. Adjust the DVM ZERO control on the computer to provide a readout of
+0. 0000 with the DVM patching terminal connected to ground. If the polar-~
ity relay begins to chatter, turn the zero control slightly clockwise until
the polarity symbol remains constant and the indicators retain the all zero
display.
3. Connect a 0 to 10 volt variable input (either polarity) to the DVM (a poten-
tiometer and inverter of the computer can be used). Slowly vary the input
level from 0 to 10 volts, and note that the DVM counting sequence is func-
tioning properly,
4. Apply a positive and then negative input (less than 11. 999 volts in each
case) to the DVM input, noting that the proper polarity sign is displayed,
If the DVM does not appear to be functioning properly, refer to Chapter 4
and correct the difficulty,
2-1
CHAPTER 2 INSTALLATION AND OPERA
2.2 NORMAL OPERATION
adout system to display voltages at se-
The DVM operates in conjunction with the computer re
ystem in
lected points. It is necessary only to address a component with the signal selector S
order to digitally display the value of an analog level. The operation of the signal selector SyS~
tem is described in the 680 Computer Maintenance Manual.
2.3 SPECIAL OPERATION
The DVM, as installed in the computer, is designed to be free-running; that is, readings are
taken continuously at a rate (50/60 cps) determined by the frequency of the ac power input,
Special applications (such as the addition of a printer or other recording device) may require
interlocking the operation of the DVM with other equipment. Built-in features of the DVM per-
mit simple external modifications to slave the operation of the meter to an external device.
The 50/60 cps trigger is jumpered from pin 3-D to pin 3-B of connector DV-P2, To supply
an external trigger, this jumper must be removed, and an external trigger may be applied to
pin 3-B of DV-P2. This trigger (or convert command) should have an amplitude of 10 volts,
(positive going), with a rise time of less than 5 microseconds. The DVM registers will con-
tain the digital equivalent of the unknown input approximately 2 milliseconds after the input
trigger (without a polarity change), or after approximately 37 milliseconds if a polarity change
is required.
A low-frequency triggering technique may also be used. The DVM contains a low-frequency
oscillator (1-3 cps) that may be used if a lower triggering rate is required. The output of this
oscillator appears on pin 3-L of DV-P2. To use this oscillator as a trigger source, the jumper
between pins 3-D and 3-B must be removed, and a jumper installed between pins 3-L and 3-B
of DV-P2.
A third triggering technique uses the high-frequency oscillator (8-10 ke) as a trigger source.
If trigger rates above 100 cps are employed, the DVM display will be difficult or impossible
to read, since the ratio of display time to conversion time decreases. If the high-frequency os-
cillator is to be used as a trigger source, the jumper between pins 3-D and 3-B of DV-P2 is re-
moved, and replaced between pins 3-C and 3-B of DV-P2, The DVM now converts continuously
at a rate of approximately 500 conversions per second, Under these conditions, the display unit
cannot provide any meaningful information. However, if a -15 volt Hold Signal is applied to pin
2-X of DV-P2, the continuous conversions are interrupted for the duration of the signal and the
TION
II cena: MMI MIMI a MMI MMM MI I I I I a I OU es OO cs OO ees I Un, OO ee: |
~
7 CHAPTER 2 INSTALLATION AND OPERATION
display may be observed. The DVM registers will contain the correct data approximately 2 mil-
liseconds after the application of the Hold signal if no polarity change was in progress, and 37
milliseconds after the Hold signal if a polarity change was in progress (i.e., if the input signal
polarity changes immediately prior to, or coincident with, the Hold command), Other signals
present at DV-P2 may be used as required by an interlocked read-print system. The Conversion
Complete signal (+2 volts when conversion is completed) is available at DV-P2, pin 2-R. Its
complement (conversion comple! ) is present at pin 2-S of DV-P2, and has a value of -12 volts
when conversion is completed.
Whenever modifications to the basic DVM system are contemplated, it is suggested that the user
contact the meanest EAI Service Engineering office for assistance. Experienced field representa-
» to offer cost-saving techniques and help to avoid potentially troublesome system
approaches. i list of the EAI Field Sales and Service Engineering offices is provided at the front
CHAPTER 3
THEORY OF OPERATION
3.1 INTRODUCTION
This chapter describes the theory of operation of the DVM in terms of a block diagram and a
functional diagram analysis. The descriptions are supplemented by block diagrams, simpli-
fied schematics, a timing diagram, functional diagrams, logic diagrams, and a power dis-
tribution diagram, Transistor theory and standard circuits incorporating these devices are
not described in detail since much written material is available on these subjects.
The DVM utilizes the programmed-comparison type of meter circuit where the current pro-
duced by the unknown (or input) voltage is compared to a known current which is the BCD
equivalent of the analog unknown; decoding the BCD count to the common decimal equivalent
provides a decimal display of the unknown magnitude. Polarity detection circuits provide a
display of the polarity sign.
3.2 BLOCK DIAGRAM DESCRIPTION
Figure 3.1 is a block diagram illustrating the operation of the DVM. The unknown input is
applied to the unloading amplifiers which provide the high input impedance of the meter as
well as the scaling of the unknown input. This unloading input system consists of two cas-
caded operational amplifiers. The first amplifier determines the scale factor given the un-
known input. The second amplifier has a fixed gain-of-one. The two amplifiers provide both
a positive and a negative polarity scaled-representation (equal in magnitude) of the input un-
known. Both polarities of the scaled unknown are applied to the polarity relay K1.
The state of the polarity relay is always set to provide the positive scaled representation of
the unknown to the comparator summing junction since it is to be compared to a known current
generated by a negative reference voltage source. The polarity of the unknown input determines
which of the two amplifiers will provide the scaled positive signal, and the polarity relay is
always switched to select this positive potential.
The proper state of the polarity relay is determined by the programmer. The programmer
temporarily removes all the known current from the comparator summing junction thus plac-
ing the comparator input entirely under the influence of the scaled unknown input as selected
CHAPTER 3
THEORY OF OPERATION
26.268 DVM
P
OLARITY COMMAND |
i
: |
| i UNKNOWN
CURRENT
a
DUAL J
UNKNOWN PO
AMPLIFIER LARITY | 33:
os DIF
INPUT [UNLOADING] | RELAY COMPARATOR [DIFFERENCE] oe aeR Pony
REET, Kl AMPLIFIER | SIGNAL DATA
|
I
== = KNOWN CLOCK
POWER SUPPLY BCD CURRENT COUNT os
STEPS PULSES VISUAL READOUT
1 1 INDICATORS
GA !
TED
+10V REF .| -100 VOLT SUMMING |. BCD GATING |8CD. COUNTERS | peciMAL
| INPUT REFERENCE RESISTOR DATA Rat oe DATA |I
eeulaeesl ECODING CKTS. 1
from one of the two input amplifiers.
set, the programmer starts the com
counters. There are four cascaded
weighted resistors.
source in BCD steps.
tude from the next lower set.
. The BC
most significant pit-weighted resis
| next most significant resistor gate
1000 bit as the lowest of that set.
weighted resisto
ing se
As each gate is opened the compar
: the known or from the
3-2
negative source in known BCD steps.
positive representation of the unknown input. The counters release the current through the
Figure 3.1. DVM, Model 26.268, Block Diagram
The comparator output level indicates to the programmer
whether the scaled unknown is positive or negative; if positive, the relay state is retained,
if negative the relay is switched to its opposite state. Drive transistors on the programmer
provide the output polarity indication for the DVM display. Once the polarity relay is properly
parison sequence by sending count pulses to the BCD
BCD counters, each controlling the gates of a set of
Each resistor set controls current flow from a known negative voltage
In addition, each of the four resistor sets differs by an order of magni-
D counters release the gates of the weighted-resistor sets and apply current from the
This current is compared to the current from the scaled
tor of the highest-order resistor set first (8000 bit), then the
a 2
of that set (4000 bit) and subsequently the 2000 bit and the
The next order counter then releases its most significant
r gate (800 bit), followed by the remaining resistors in that set. The count
quence thus proceeds through all the resistors in the four sets in the same order
ator indicates to the BCD counters whether the current from
unknown is the larger. If the wnknown current is larger, the opened gat
e
CHAPTER 3 THEORY OF OPERATION
remains opened (its counter remains on) when the next gate is released. If the known current
is larger, the gate is closed (its counter turned off) when the succeeding gate is opened, Using
this programmed-comparison sequence of operation, the known and unknown currents are brought
into agreement in magnitude.
The counters that are still on when agreement is reached and the counting cycle is completed,
contain in BCD count the magnitude of the unknown input. This data is decoded into the decimal
form to be displayed as the magnitude of the unknown input on the visual readout.
3.3 DVM CIRCUIT DESCRIPTIONS
Functional Schematic Diagram D026 268 0S (Sheets 1, 2, and 3) in Appendix 2 is used as the
basis of the DVM circuit description. This diagram is supplemented by detailed schematic
diagrams of each etched-circuit card, also in Appendix 2. In addition, a logic flow diagram,
a timing diagram, and simplified schematic diagrams are incorporated within the text.
The DVM circuit description is described assuming the DVM is measuring an input voltage of
44,507 volts. In order to enable the reader to more easily follow the digitizing sequence of the
DVM, the input unloading amplifier circuits, and the comparator and gated resistor matrix are
briefly described first.
8.3.1 Unloading Amplifiers
Figure 3.2 is a simplified schematic of the unloading amplifier circuit of the DVM. The dual
amplifier configuration permits the DVM to measure both positive and negative inputs, and also
provides the high input impedance of the DVM readout system. The gain of amplifier A is nor-
mally 1.25, thus permitting unloading of the input circuit. Whena D/10 readout is required, an ex-
ternal connection is completed between pins 3-H and 3-K of J1, changing the gain of amplifier
Ato 0,125. The gain of amplifier B is unity; therefore, both amplifiers provide scaled outputs
of the unknown (equal in magnitude but of opposite polarity) to the K1 polarity relay. The amp-
lifier A output is applied to K1-6, the amplifier B output is applied to K1-5. During the Zero
Set and Sign Check sequence in the DVM operation (described later in the text), the position of
the Ki armature is set so the positive scaled representation of the unknown is applied to the
comparator summing junction,
An anti-saturation network is provided around amplifier A to prevent saturation of this unit
during overload conditions. This decreases the amplifier recovery time when the overload
is removed.
3-3
CHAPTER 3 THEORY OF OPERATION
R4
Ri—| } R4p
-. 24.9k a
RI-4
«KZ
3-K qT AA R22
! 125K , POLARITY
NI Wh
1 13.889K 1 2 TO
\ COMPARATOR
! RS 34 VIA FULL
syd! RI-2 R21 8 SCALE CIRCUIT
= NW —4
100K 10K
ANTI-
| SATURATION
CIRCUIT
NOTE:
RELAY KI SHOWN DE-ENERGIZED
Figure 3.2. Input Unloading Amplifiers, Simplified Schematic
3.3.2 Comparator Amplifier and Gated Resistor Matrix
The comparator amplifier is a high-gain unit sensitive to the polarity of the source of the com-
parator summing junction current, It consists of a four stage differential amplifier (Q1 through
Q4 of the 26. 240) and two cascaded output stages, Q5 and Q6, The output stages operate at
either saturation (0 volt out) or at cutoff (-14 volts out) in response to the polarity of the sum-
ming junction current source; the output of Q5 is the Comp + output and that of Q6 the Comp -
output. The two outputs are opposite in phase. The DVM only uses the Comp - output (referred
to hereafter as the comparator output or Comp Out).
The comparator output is negative (-14 volts) when the comparator summing junction current
is due to a positive polarity source, and the output is positive (0 volt) when the summing junction
current is due to a negative polarity source.
In addition to the output of one of the dual de amplifiers (via K1), the gated resistor Pabebeds
also connected to the comparator summing point. The gated resistor matrix is provided with
a -100 volt reference source. The polarity of the comparator output indicates whether the
current due to the unknown at the summing junction is larger (negative comparator output) or
if the matrix current is larger (positive comparator output or zero volt level).
paels
_—t
|
re
CHAPTER 3 THEORY OF OPERATION
Le
The current from the negative reference source is divided into binary-coded decimal steps by
=
Ta
the use of matched resistor sets. A typical example is illustrated in Figure 3.3 which shows
four resistors, each gated, and each gate controlled by a separate BCD counter. (The BCD
counters of the 100's decade are shown in this illustration.) The 125K resistor permits eight
times the current flow as that permitted by the 1 megohm resistor and so on in the ratio of
8:4:2:1 as indicated by the parenthetical notations in Figure 3.3, If three more sets of four
_ resistors (each set ratioed to the next by an order of magnitude) are added to this group and
controlled by the 1000's, 10's and 1's counter, then the BCD count of each decade of the DVM
will determine the precise current flow from the negative source to the comparator summing
_ point,
“LL
-I00V \
Li
REFERENCE 7
(8) (4) (2) $ “)
125K 250K > 500K > 1 MEG
A
= q— <— 800 COUNTER
x
pact <— 400 COUNTER
—_ c!
o—_q—_}——_——=—-. 200 CounTER
D'
o—qd—<— 100 COUNTER
[ A B i P
| I
I |
[ _ FROM 0C R |
1
KS COMP +
_j (NOT USED)
y Vv
f+
RI
DIFFERENTIAL | COMPARATOR TO
AMPLIFIER wn {& 4} AMPLIFIER 23> ae> OUTPUT > PROGRAMMER
VIA KI | Q1-Q4 1° (comP-) AND COUNTERS
|
L
cel
RIO
+40V
ref
Figure 3.3. Comparator and Typical Gated Resistor Matrix, Simplified Schematic
3-5
—
CHAPTER 3
THEORY OF OPERATION - ]
=
\
] Th : :)
| © current from the ~100 volt reference source is compared to that from the positive repre~ |
sentation of the unknown input at the comparator summing junction, The larger of the two, =
by determining the comparator output polarity, permits the DVM to bring the reference cur- —
rent int i
| into agreement with the unknown current, —— wl
) ; y
When this state is attained, the count in the BCD counters is the numerical equivalent of the
| snknown input magnitude in binary-coded decimal form, al
The counters control the reference current flow to the comparator summing junction by either
. A _ _
forward biasing or reverse biasing the diode gates of the resistor matrix, For example, if
the 800 counter applies a +2 volt potential to diode A', then diode A is forward biased and the vy
current through the 125K resistor cannot reach the comparator summing point. If the 800 —— om
counter applies a -10 volt potential to A! » the A' is reverse biased and the current through the
125K resistor flows through diode A to the comp
arator,
— ee
3.3.3 DVM Sampling Cycle —a
—— Oe
The following logic description covers the overall operation of the DVM
during a sampling cycle
as previously mentioned, that the polarity of r a
The operating cycle is divided into three parts: 1) Zero Set and bre
2) Digitizing Cycle (these two parts of the operating cycle make up the conver- Ibe
sion cycle), and 3) Display Cycle. sa
| of the unknown input. This description assumes,
the input does not change,
Polarity Check
To make the description meaningfu